xr16m580im48 Exar Corporation, xr16m580im48 Datasheet
xr16m580im48
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TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO SEPTEMBER 2008 GENERAL DESCRIPTION 1 The XR16M580 (M580 enhanced Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable transmit and receive FIFO trigger ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO IGURE IN UT SSIGNMENT DSR# 25 CD# 26 RI# 27 32- pin QFN in VCC ...
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... IGURE IN UT SSIGNMENT OR A1 Corner CTS# VCC ORDERING INFORMATION P N ART UMBER XR16M580IL32 XR16M580IM48 XR16M580IB25 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 25- BGA P PIN ACKAGE Transparent Top View RESET INT A1 16/68# RTS# A0 ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN DATA BUS INTERFACE ...
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REV. 1.0.0 Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN RTS CTS DTR DSR CD RI ANCILLARY SIGNALS XTAL1 10 14 ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN 15 10, 12, 17, 20- 25, 29, 31, 34, 36, 37, 48 Pin ...
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REV. 1.0.0 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The M580 data interface supports the Intel and motorola ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.2 Serial Interface The M580 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information ...
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REV. 1.0 XR16M580 T S IGURE YPICAL ERIAL DTR# UART 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO I C NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.3 Device Reset The RESET input resets the internal registers and the serial interface outputs to their default state (see Table 16). An active high pulse of longer than 40 ...
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REV. 1.0.0 2.6 Crystal Oscillator or External Clock Input The M580 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.7 Programmable Baud Rate Generator with Fractional Divisor The M580 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver. The prescaler is controlled by a software ...
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REV. 1.0 IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 2.8 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every ...
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REV. 1.0.0 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 11 IGURE ECEIVER PERATION IN NON 16X Clock ( DLD[5:4] ) Receive Data Byte and Errors F 12 IGURE ECEIVER PERATION ...
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REV. 1.0.0 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-asserted (LOW), indicating more data may be ...
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REV. 1.0.0 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M580 will halt transmission (TX) as soon as ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the receiver if the address matches its slave address, otherwise, it does ...
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REV. 1.0 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and Power-Save feature The M580 supports low voltage system ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO an interrupt is pending from any channel. The M580 will stay in the sleep mode of operation until it is disabled by setting IER bit logic 0. A ...
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REV. 1.0.0 2.18 Internal Loopback The M580 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 15 shows ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 3.0 UART INTERNAL REGISTERS The complete register set for the M580 is shown in T ABLE DDRESSES DREV - Device Revision 0 0 ...
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REV. 1.0 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DREV RD Bit ...
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REV. 1.0.0 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect the ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO IER[4]: Sleep Mode Enable (requires EFR[ • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. ...
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REV. 1.0.0 • Special character interrupt is cleared by a read to ISR register or after next character is received. See EMSR[7]. • RTS# and CTS# flow control interrupts are cleared by a read to the MSR register. • Wakeup ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and enable the wake up interrupt. ...
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REV. 1.0 ABLE RANSMIT AND FCR B -7 FCR B -6 FCR 4.6 Line Control Register (LCR) - Read/Write The ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • ...
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REV. 1.0.0 MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used as ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit 1 ...
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REV. 1.0.0 4.9 Modem Status Register (MSR) - Read Only This register provides the current state of the modem interface input signals. Lower four bits of this register are used to indicate the changed information. These bits are set to ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M580. Lower four bits of this register are reserved. Writing to the higher four bits ...
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REV. 1.0.0 4.12 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.13 Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write These registers make-up the value of the baud rate divisor. The M580 has different DLL, DLM and DLD for ...
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REV. 1.0.0 4.14 RX/TX FIFO Level Count Register (FC) - Read-Only This register replaces SPR (during a read) and is accessible when FCTR[ This register is also accessible when LCR = 0xBF suggested to read the ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.16 Enhanced Feature Register (EFR) - Read/Write Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive character software flow control selection (see are ...
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REV. 1.0.0 EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match exists, ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO REGISTERS DLM, DLL (Both TX and RX) DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FC FCTR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# ...
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REV. 1.0.0 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (32-QFN) Thermal Resistance (48-TQFP) Thermal Resistance (25-BGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO PAGE 22. To achieve minimum power drain, the voltage at any of the inputs of the M580M580 should NOT be lower than its VCC supply. AC ELECTRICAL CHARACTERISTICS O O ...
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REV. 1.0.0 AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay To Set Interrupt From MODEM MOD Input T Delay To Reset Interrupt From IOR# RSI T ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 17 IGURE ODEM NPUT UTPUT ...
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REV. 1.0 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 21 IGURE ODE OTOROLA A0-A2 T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start ...
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REV. 1.0 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO F 25 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up to ...
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REV. 1.0.0 PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO ) ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.0.0 PACKAGE DIMENSIONS (25 PIN BGA - 0.8 Seating Plane Note: The control dimension is the millimeter column SYMBOL 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO ...
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... Rev 1.0.0 Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16M580 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN ...
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XR16M580 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 27 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 28 T ...