xr16m564 Exar Corporation, xr16m564 Datasheet
xr16m564
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xr16m564 Summary of contents
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... Motorola processors. The XR16M564IV (64-pin) offers three state interrupt output while the XR16M564DIV provides continuous interrupt output. The XR16M564 is compatible with the industry standard ST16C554 and ST16C654/ 654D ...
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... DTRC# CTSB CTSC# DSRB DSRC# XR16M564 64-pin TQFP Intel Mode Only 2 REV. 1.0.0 64- LQFP P ODE AND PIN ACKAGES 60 DSRD# 59 CTSD# 58 DTRD# 57 GND 56 RTSD# 55 N.C. XR16M564 54 N.C. 68-pin PLCC 53 TXD 52 N.C. Motorola Mode 51 TXC N.C. 48 RTSC# 47 VCC 46 DTRC# 45 CTSC# 44 DSRC# 48 DSRD# 47 CTSD# 46 DTRD# ...
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... XR16M564 6 31 48-pin QFN 16M 564 80 - pin LQFP Intel Mode Only 3 XR16M564/564D ACKAGE RXD CTSD# GND RTSD# INTD CSD# TXD IOR# TXC CSC# INTC RTSC DC# 58 RIC# 57 RXC 56 GND TXR DY# ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO ORDERING INFORMATION P N ART UMBER XR16M564IJ68 XR16M564IV64 XR16M564DIV64 XR16M564IL48 XR16M564IV80 PIN DESCRIPTIONS Pin Description 48-QFN 64-LQFP 68-PLCC N AME DATA BUS INTERFACE ...
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... Transmitter Ready (active low). This output is a logi- cally ANDed status of TXRDY# A-D. See this output is unused, leave it unconnected Receiver Ready (active low). This output is a logically ANDed status of RXRDY# A-D. See output is unused, leave it unconnected. 5 XR16M564/564D D ESCRIPTION Table 5. If Table 5. If this ...
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... See MCR bit-3 descrip- tion for full detail. This pin must be LOW in the Motor- ola bus interface mode. For the 64 pin packages, this pin is bonded to VCC internally in the XR16M564D so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the XR16M564 and therefore requires setting MCR bit-3 for enabling the interrupt output pins ...
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... Motorola bus interface is not available on the 64 pin package. 5, 25, 45, Pwr 1.62V to 3.63V power supply 16, 36, Pwr Power supply common, ground XR16M564/564D D ESCRIPTION Figure 6 in the Baud Rate Generator 17). When 16/68# pin is at LOW for ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO Pin Description 48-QFN 64-LQFP 68-PLCC N AME GND Center N/A Pad N. Pin type: I=Input, O=Output, I/O= Input/Output, OD=Output Open Drain. 80-LQFP T YPE N/A N/A Pwr The center pad on the backside of the QFN package is metallic and should be connected to GND on the PCB. ...
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... Xon/Xoff and special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of dividing and data rate Mbps. The XR16M564 can operate from 1.62 to 3.63 volts. The M564 is fabricated with an advanced CMOS process. ...
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... UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown XR16M564 T I IGURE YPICAL NTEL ...
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... Channel A selected Channel B selected Channel C selected Channel D selected Channels A-D selected See Table A HANNEL ELECT UNCTION X X UART de-selected 0 0 Channel A selected 0 1 Channel B selected 1 0 Channel C selected 1 1 Channel D selected 11 XR16M564/564D Table 1. ODE ODE ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 2.4 Channels A-D Internal Registers Each UART channel in the M564 has a set of enhanced registers for controlling, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers ...
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... LOW = FIFO empty LOW = FIFO has at least 1 empty location HIGH = at least 1 byte in FIFO HIGH = FIFO is full R=300K to 400K XTAL1 14.7456 XTAL2 MHz C2 C1 22-47pF 22-47pF 16 - 0.0625) in increments of 0.0625 (1/16 XR16M564/564D C A-D ODE FOR HANNELS ) NABLED FCR (DMA ODE NABLED ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a value from 0 (for setting 0000 ...
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... XR16M564/564D 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1 ...
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... Errors 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO Figure 9 and Figure 10 below. -FIFO M ODE Receive Data Shift Data Bit Register (RSR) Validation Error Receive Data Tags in Holding Register RHR Interrupt (ISR bit-2) LSR bits (RHR) 4:2 17 XR16M564/564D Receive Data Characters RXFIFO1 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO F 10 IGURE ECEIVER PERATION IN 16X lock ( D LD [5: eceive D ata Shift R egister ( bytes by 11-bit w ide FIFO R eceive D ata Byte and Errors 2.11 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission ...
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... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 19 XR16M564/564D Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 2.14 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M564 will halt transmission (TX) as soon as the current character has completed transmission ...
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... TO 3.63V QUAD UART WITH 32-BYTE FIFO Figure 12 below. Figure 12 NCODING AND ECEIVE ATA ECODING Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 21 XR16M564/564D 1 0 1/2 Bit Time IrEncoder IRdecoder-1 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 2.17 Sleep Mode with Auto Wake-Up The M564 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the M564 to enter sleep mode: no interrupts pending for all four channels of the M564 (ISR bit ■ ...
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... L B IGURE NTERNAL OOP ACK IN Transmit Shift Register Receive Shift Register 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO HANNELS VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# OP2# CD# 23 XR16M564/564D TX A-D RX A-D RTS# A-D CTS# A-D DTR# A-D DSR# A-D RI# A-D CD# A-D ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each UART channel in the M564 has its own set of configuration registers selected by address lines A0, A1 and A2 with a specific channel selected (See Table 9 and Table 10 UART CHANNEL A AND B UART INTERNAL REGISTERS ...
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... CTS# Delta Input Input Input CD# Bit-6 Bit-5 Bit-4 Bit-3 Baud Rate Generator Divisor Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Rsvd 4X Mode 8X Mode Bit-3 25 XR16M564/564D EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX Stat ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO T 10: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE EFR RD/WR Auto CTS# Enable XON1 RD/WR Bit XON2 RD/WR Bit XOFF1 RD/WR Bit XOFF2 RD/WR Bit-7 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read- Only SEE” ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M564 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1) • Logic 0 = Disable the RTS# interrupt (default). • Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition from LOW to HIGH (if enabled by EFR bit-6). ...
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... LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) 29 XR16M564/564D L EVEL S OURCE OF INTERRUPT ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO FCR[1]: RX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic receive FIFO reset (default) • Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not cleared or altered) ...
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... Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The receiver must be programmed to check the same format. 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO BIT-0 W ORD LENGTH 0 5 (default TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7,8 1 (default) 5 1-1/2 6,7 XR16M564/564D ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = LOW, parity is not forced (default). • LCR BIT-5 = HIGH and LCR BIT-4 = LOW, parity bit is forced to a logical 1 for the transmit and receive data. ...
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... Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth. 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO T 14: INT O M ABLE UTPUT ODES MCR INT A UTPUTS IN ODE Three-State 1 Active X Active Figure 33 XR16M564/564D 13. ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 4.8 Line Status Register (LSR) - Read/Write This register is writeable but it is not recommended. The LSR provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an error is in the RHR ...
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... Scratch Pad Register (SPR) - Read/Write This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle. XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 35 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL gives the 16-bit divisor value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be enabled via EFR bit-4 before it can be accessed. See 2.8, Programmable Baud Rate Generator with Fractional Divisor” ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 37 XR16M564/564D ECEIVE OFTWARE LOW ONTROL ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts HIGH at the next upper trigger level/hysteresis level ...
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... Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 RESET STATE HIGH HIGH HIGH HIGH LOW XR16M564 = Three-State Condition (INTSEL = LOW) XR16M564 = LOW (INTSEL = HIGH) XR16M564D = LOW Three-State Condition (INTSEL = LOW) 39 XR16M564/564D ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-QFN) Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) Thermal Resistance (80-LQFP) ELECTRICAL CHARACTERISTICS ...
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... XR16M564/564D L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay To Reset Interrupt From IOR# RSI T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset Interrupt RRI T Delay From Start To Interrupt SI T Delay From Initial INT Reset To ...
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... RDV Valid Data 43 XR16M564/564D Valid Address T ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO F 17 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# T RDA D0- A-D US RITE IMING FOR HANNELS ...
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... T [N -FIFO M ] IMING ON ODE FOR Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready XR16M564/564D A-D Valid Address Valid Data 68Write C A-D HANNELS D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...
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... SSI T SSR T [FIFO M , DMA M IMING ODE Stop Bit T D0:D7 S D0:D7 S D0: below trigger level T WRI 47 XR16M564/564D ] C A-D FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXFIFODMA A-D ODE ISABLED FOR HANNELS Last Data Byte ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO F 25 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0:D7 S D0:D7 T (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data into FIFO) *INT cleared when the ISR is read or when TX FIFO fills up to trigger level. ...
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... Note: The actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm. The lead may be half-etched terminal. INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.270 0.281 6.85 0.201 0.209 5.10 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.012 0.020 0.30 0.008 - 0.20 49 XR16M564/564D MAX 1.00 0.05 0.25 7.15 5.30 0.30 0.50 - ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 64 LEAD LOW-PROFILE QUAD FLAT PACK ( 1.4 mm LQFP) A Seating Plane Note: The control dimension is the millimeter column SYMBOL α INCHES MILLIMETERS MIN ...
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... BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 51 XR16M564/564D C Seating Plane 45 ° MAX 5.08 3.30 --- 0.53 0.81 0.32 25.27 24.33 23.62 1.42 1.22 1.14 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 80 LEAD PLASTIC QUAD FLAT PACK ( LQFP, 1.4 mm Form) Note: The control dimension is the millimeter column SYMBOL α p INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO REVISION HISTORY D R ATE EVISION August 2007 Rev P1.0.0 Preliminary Datasheet. May 2008 Rev 1.0.0 Final Datasheet. Updated DC and AC Electrical Characteristics. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...
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... REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 F .................................................................................................................................................... 1 EATURES A .............................................................................................................................................. 1 PPLICATIONS F 1. XR16M564 B D IGURE LOCK IAGRAM IGURE IN UT SSIGNMENT IGURE IN UT SSIGNMENT OR PIN DESCRIPTIONS ........................................................................................................ 4 ............................................................................................................................... 4 ORDERING INFORMATION 1.0 PRODUCT DESCRIPTION ...................................................................................................................... 9 2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 10 2.1 CPU INTERFACE .............................................................................................................................................. XR16M564 IGURE YPICAL NTEL 2 ...
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... XR16M564/564D 1.62V TO 3.63V QUAD UART WITH 32-BYTE FIFO 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 28 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 28 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 31 ...