xr16m680 Exar Corporation, xr16m680 Datasheet
xr16m680
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xr16m680 Summary of contents
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... QFN, 48-pin TQFP and 25-pin BGA packages. All three packages offer both the 16 mode (Intel bus) interface and the 68 mode (Motorola bus) interface which allows easy integration processors OTE 1 Covered by U.S. Patent #5,649,122 XR16M680 B D IGURE LOCK IAGRAM Pw rSave A2:A0 D7:D0 IOR# IOW # (R/W #) CS# INT (IRQ#) Intel or ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO IGURE IN UT SSIGNMENT DSR# 25 CD# 26 RI# 27 32- pin QFN in VCC 28 Intel Bus Mode VCC ...
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... Transparent Top View RESET INT A1 16/68# RTS PwrSave PERATING P ACKAGE 32-pin QFN -40°C to +85°C 48-Lead TQFP -40°C to +85°C 25-Pin BGA -40°C to +85°C 3 XR16M680 A2 IOR# IOW# XTAL1 GND T EMPERATURE D S EVICE TATUS R ANGE Active Active Active ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN DATA BUS INTERFACE IOR IOW# ...
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... GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. 5 XR16M680 D ESCRIPTION ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN 15 10, 12, 17, 20- 25, 29, 31, 34, 36, 37, 48 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. T YPE # Connects REV. 1.0.0 D ESCRIPTION ...
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... Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps. The XR16M680 can operate from 1.62 to 3.63 volts. The M680 is fabricated with an advanced CMOS process. ...
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... The M680 data interface supports the Intel and Motorola compatible types of CPUs. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure XR16M680 T I IGURE YPICAL NTEL D0 D1 ...
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... Serial Interface The M680 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com or send an e-mail to uarttechsupport@exar.com XR16M680 T S IGURE YPICAL ERIAL ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 6. XR16M680 T S IGURE YPICAL ERIAL DTR# UART NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# DSR# CD GND RS-485 Half-Duplex Serial Interface ...
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... PERATION FOR ECEIVER ) FCR B ISABLED LOW = FIFO below trigger level HIGH = FIFO above trigger level or RX Data Timeout HIGH = FIFO below trigger level LOW = FIFO above trigger level or RX Data Timeout 11 XR16M680 Table 1 and 2 Figure 22 through 25 (FIFO NABLED - (FIFO E ) ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.6 Crystal Oscillator or External Clock Input The M680 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock for bus operation ...
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... Independent TX/RX BRG The XR16M680 has two independent sets of TX and RX baud rate generator. Please see the RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting, please See ” ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) ...
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... T O IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock ( DLD[5:4] ) 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M680 TXNOFIFO1 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty ...
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... FIFO is Enabled bit-0=1 D ata fills to R TS# de-asserts w hen data fills above the flow 24 control trigger level to suspend rem ote transm itter. Enable by EFR bit-6= bit-1. R eceive D ata 17 XR16M680 Receive Data Characters RXFIFO1 M ODE R eceive D ata C haracters R X FIFO 1 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...
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... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 19 XR16M680 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M680 will halt transmission (TX) as soon as the current character has completed transmission ...
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... Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO Figure 14 below. 21 XR16M680 Figure 14. ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 14 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and Power-Save feature The M680 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save feature is included to reduce its power consumption when the chip is not actively used ...
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... The M680 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The default status of wake up interrupt is disabled. Please Write-Only” on page 31. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO Figure 1 on page See ”Section 4.5, FIFO Control Register (FCR XR16M680 1) from other bus activities that ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 2.18 Internal Loopback The M680 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 15 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... Write-only Read-only E R NHANCED EGISTERS Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 25 XR16M680 /W C RITE OMMENTS LCR[ LCR ≠ 0xBF, DLL = 0x00, DLM = 0x00 LCR[ LCR ≠ 0xBF See DLD[7:6] LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR[ EFR[ LCR ≠ 0xBF if EFR[ LCR ≠ ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
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... ISR [5:4], Flow FCR[5:3], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 27 XR16M680 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 LCR[ LCR≠0xBF DLL= 0x00 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M680 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control. • RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control. • Wakeup interrupt is generated when the M680 wakes up from the sleep mode. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 29 XR16M680 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading RHR. • ...
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... Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 23. Table 9 below shows the selections. Note that the Table 9 31 XR16M680 shows the complete selections. ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO ABLE RANSMIT AND FCR B -7 FCR B -6 FCR 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO S W TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7,8 1 (default) 5 1-1/2 6,7 10: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 33 XR16M680 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains, until disabled by setting LCR bit logic 0. ...
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... LSR[3]: Receive Data Framing Error Tag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO Figure 35 XR16M680 15. ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “ ...
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... MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M680. Lower four bits of this register are reserved. Writing to the higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter (Requires EFR[ • ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.12 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in ...
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... Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for TX. Transmitter and Receiver uses different BRGs. Writing to DLL, DLM and DLD[5:0] configures the BRG for RX. Transmitter and Receiver uses same BRG. 39 XR16M680 See ”Section 2.7, Programmable Table 13 below ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.14 RX/TX FIFO Level Count Register (FC) - Read-Only This register replaces SPR (during a read) and is accessible when FCTR[ This register is also accessible when LCR = 0xBF suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 41 XR16M680 ECEIVE OFTWARE LOW ONTROL ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘ ...
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... Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 7-0 =0xX0 (Read-only) Bits 7-4 = 0000 (Write-only) Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 RESET STATE HIGH HIGH HIGH Three-State Condition HIGH 43 XR16M680 ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (32-QFN) Thermal Resistance (48-TQFP) Thermal Resistance (25-BGA) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS ...
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... XR16M680 L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER T Delay To Set Interrupt From MODEM MOD Input T Delay To Reset Interrupt From IOR# RSI T Delay From Stop To Set Interrupt SSI T Delay From IOR# To Reset Interrupt ...
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... RDV Valid Data 47 XR16M680 Valid Address T ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 19 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- RITE IMING ...
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... Valid Data T [N -FIFO M ] IMING ON ODE Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready XR16M680 Valid Address Valid Data 68Write D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO F 23 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...
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... ISR is read or when TX FIFO fills up to the trigger level. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO T [FIFO M ] IMING ODE Stop Bit D0:D7 D0:D7 T D0: below trigger level T WRI 51 XR16M680 Last Data Byte Transmitted D0: D0:D7 T ISR is read T SRT TX FIFO Empty TX FIFO drops TXDMA# ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 ...
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... INCHES MILLIMETERS MIN MAX MIN 0.039 0.047 1.00 0.002 0.006 0.05 0.037 0.041 0.95 0.007 0.011 0.17 0.004 0.008 0.09 0.346 0.362 8.80 0.272 0.280 6.90 0.020 BSC 0.50 BSC 0.018 0.030 0.45 0× 7× 0× 53 XR16M680 α L MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10 0.75 7× ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO PACKAGE DIMENSIONS (25 PIN BGA - 0.8 Seating Plane Note: The control dimension is the millimeter column SYMBOL (A1 corner feature is mfger option INCHES MILLIMETERS ...
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... Copyright 2008 EXAR Corporation Datasheet September 2008. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO D ESCRIPTION NOTICE 55 XR16M680 ...
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... PRODUCT DESCRIPTION ...................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8 2.1 CPU INTERFACE ................................................................................................................................................ XR16M680 IGURE YPICAL NTEL 2.2 SERIAL INTERFACE........................................................................................................................................... XR16M680 T S IGURE YPICAL ERIAL F 6. XR16M680 T S IGURE YPICAL ERIAL 2.3 DEVICE RESET ................................................................................................................................................. 11 2.4 INTERNAL REGISTERS.................................................................................................................................... 11 2.5 INT OUPUT ........................................................................................................................................................ INT ABLE IN PERATION FOR RANSMITTER T 2: INT P ...
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... XR16M680 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 28 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 29 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 29 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ...