xr16m698 Exar Corporation, xr16m698 Datasheet

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xr16m698

Manufacturer Part Number
xr16m698
Description
1.62v To 3.63v High Performance Octal Uart With 32-byte Fifo
Manufacturer
Exar Corporation
Datasheet

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xr16m698IQ100-F
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xr16m698IQ100-F
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MAY 2008
GENERAL DESCRIPTION
The XR16M698
Universal Asynchronous Receiver and Transmitter
(UART). The highly integrated device is designed for
high
systems.
provides a complete interrupt status indication for all
8 channels to speed up interrupt parsing. Each UART
has its own 16C550 compatible set of configuration
registers, TX and RX FIFOs of 32 bytes, fully
programmable transmit and receive FIFO trigger
levels, automatic RTS/CTS or DTR/DSR hardware
flow control with programmable hysteresis, automatic
software (Xon/Xoff) flow control, RS-485 half-duplex
direction control with programmable turn-around
delay, Intel or Motorola bus interface and sleep mode
with a wake-up indicator.
N
APPLICATIONS
Exar
F
OTE
IGURE
Remote Access Servers
Ethernet Network to Serial Ports
Network Management
Factory Automation and Process Control
Point-of-Sale Systems
Multi-port RS-232/RS-422/RS-485 Cards
: Covered by US patents #5,649,122 and #5,949,787
Corporation 48720 Kato Road, Fremont CA, 94538
16/68#
IOR#
CS#
INT#
RST#
A7:A0
D7:D0
IOW#
bandwidth
1. B
The
LOCK
1
global
D
(698), is a 1.62V to 3.63V octal
requirement
Data Bus
Interface
IAGRAM
1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO
interrupt
in
Timer/Counter
Configuration
source
Registers
communication
Device
16-bit
register
(510) 668-7000
FEATURES
1.62V to 3.63V supply voltage
Single Interrupt output for all 8 UARTs
A Global Interrupt Source Register for all 8 UARTs
5G “Flat” UART Registers for easier programming
Simultaneous Initialization of all UART channels
General Purpose 16-bit Timer/counter
Sleep Mode with Wake-up Indication
Highly Integrated Device for Space Saving
Each UART is independently controlled with:
Up to 15 Mbps Serial Data Rate
Pin
XR16V798 and XR16M598
UART
Regs
BRG
16C550 Compatible 5G Register Set
32-byte Transmit and Receive FIFOs
Fractional Baud Rate Generator
Programmable TX and RX FIFO Trigger Level
Automatic RTS/CTS or DTR/DSR Flow Control
Automatic Xon/Xoff Software Flow Control
RS-485 Half-Duplex Direction Control Output
with Selectable Turn-around Delay
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
UART Channel 1
UART Channel 2
UART Channel 3
UART Channel 4
UART Channel 5
Crystal Osc/Buffer
UART Channel 0
UART Channel 6
UART Channel 7
compatible
TX & RX
32 Byte TX FIFO
32 Byte RX FIFO
FAX (510) 668-7017
ENDEC
IR
to
XR16V698,
XR16M698
DSR0#, RTS0#,
TX0, RX0, DTR0#,
CTS0#, CD0#, RI0#
XTAL1
XTAL2
TMRCK
DSR7#, RTS7#,
TX7, RX7, DTR7#,
CTS7#, CD7#, RI7#
www.exar.com
XR16V598,
REV. 1.0.0

Related parts for xr16m698

xr16m698 Summary of contents

Page 1

... TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO MAY 2008 GENERAL DESCRIPTION 1 The XR16M698 (698 1.62V to 3.63V octal Universal Asynchronous Receiver and Transmitter (UART). The highly integrated device is designed for high bandwidth requirement in systems. The global interrupt provides a complete interrupt status indication for all 8 channels to speed up interrupt parsing ...

Page 2

... ORDERING INFORMATION ART UMBER XR16M698IQ100 100-Lead QFP XR16M698 100-QFP ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. 1.0.0 ...

Page 3

... I XR16M698 device. When 16/68# pin is LOW, this input becomes the read and write strobe (active LOW) for the Motorola bus interface. Global interrupt output from XR16M698 (open drain, active LOW). This output INT requires an external pull-up resistor (47K-100K ohms) to operate properly. It may be shared with other devices in the system to form a single interrupt line to the host pro- cessor and have the software driver polls each device for the interrupt status ...

Page 4

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO AME IN YPE UART channel 0 Ring Indicator or general purpose input (active LOW). RI0 UART channel 1 Transmit Data or infrared transmit data. TX1 85 O UART channel 1 Receive Data or infrared receive data. Normal RXD input idles ...

Page 5

... UART channel 6 Data Set Ready or general purpose input (active LOW). See DSR6 description of DSR0# pin. UART channel 6 Carrier Detect or general purpose input (active LOW). CD6 UART channel 6 Ring Indicator or general purpose input (active LOW). RI6 UART channel 7 Transmit Data or infrared transmit data. TX7 ESCRIPTION 5 XR16M698 ...

Page 6

... I a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 8 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit-6 in the UART. Reset (active LOW). The XR16M698 does not have a Power-on reset. Therefore, a RST hardware reset must be issued using this pin during power-up. The configuration and UART registers are reset to default values, see Intel or Motorola data bus interface select ...

Page 7

... REV. 1.0.0 1.0 DESCRIPTION The XR16M698 (698) integrates the functions of 8 enhanced 16550 UARTs, a general purpose 16-bit timer/ counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt source registers that provides interrupt-status for all 8 UARTs, timer/counter and a sleep wake up indicator. ...

Page 8

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.3 Simultaneous Write to All Channels During a write cycle, the setting of the Device Configuration register REGB override the channel selection of address A6:A4 and allow a simultaneous write to all 8 UART channels when any channel is written to. This functional capability allow the registers in all 8 UART channels to be modified concurrently, saving individual channel initialization time. Caution should be considered, however, when using this capability. Any in-process serial data transfer may be disrupted by changing an active channel’ ...

Page 9

... Figure 3. For further reading on oscillator circuit please 3. T YPICAL OSCILLATOR CONNECTIONS R=300K to 400K XTAL2 XTAL1 24 MHz C1 C2 22-47pF 22-47pF 16 - 0.0625) in increments of 0.0625 (1/16) to shows the standard data rates available with a 24MHz crystal or 9 XR16M698 9. Figure 3). Alternatively, an external ...

Page 10

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 8XMODE [7: Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16) X 4XMODE [7: 8XMODE [7: Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate 4XMODE [7: 8XMODE [7: ...

Page 11

... Register or 4XMODE Register) internal clock. A bit time XR16M698 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX)) R (%) ALUE ATE ...

Page 12

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.7.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s) ...

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... RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4. FIFO AND LOW ONTROL ODE Transmit THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transmit Data Shift Register (TSR) 13 XR16M698 ...

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... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO IGURE ECEIVER PERATION IN NON 16X Clock Receive Data Byte and Errors IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) 32 bytes by 11-bit ...

Page 15

... Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Figure 9 15 XR16M698 , 16C550 COMPATIBLE Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 ...

Page 16

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.10.1 Auto CTS/DSR Flow Control Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit specific application requirement (see • ...

Page 17

... TXB RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend RTS High RTS Low 5 Threshold Threshold 17 XR16M698 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...

Page 18

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.11 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled ( characters with the programmed Xon-1,2 or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed Xoff-1,2 value(s), the 698 will halt transmission (TX) as soon as the current character has completed transmission ...

Page 19

... If another address byte is received and this address does not match the programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity bit in the parity error bit. Table asserts RTS# or DTR# 19 XR16M698 ...

Page 20

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.14 Infrared Mode Each UART in the 698 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 8 UART channels to start up in the infrared mode ...

Page 21

... A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. The number of characters lost during the restart also depends on your operating data rate. More characters are lost when operating at higher data rate. 21 XR16M698 ...

Page 22

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO 2.16 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...

Page 23

... XR16M698 REGISTERS The XR16M698 octal UART register set consists of the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and monitoring the status of various functions. These functions include all 8 channel UART’s interrupt control and status, 16-bit general purpose timer control and status, sleep mode, soft-reset, and device identification and revision ...

Page 24

... UART channel 4 Registers 0x50 - 0x5F UART channel 5 Registers 0x60 - 0x6F UART channel 6 Registers 0x70 - 0x7F UART channel 7 Registers 0x80 - 0x8F Device Configuration Registers , and device identification and revision XR16M698 R S ABLE EGISTER ETS S R PACE EFERENCE Table & ...

Page 25

... REGB 0 3.1.1 The Global Interrupt Source Registers The XR16M698 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1, INT2 and INT3]. The four registers are in the device configuration register address space. INT3 [0x00] All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 8 channel interrupts are enabled or disabled in each channel’ ...

Page 26

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents channel 0 and bit-7 indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR, LSR and MSR). SEE” ...

Page 27

... Timer interrupt pending and 0x00 at all other times. [7: HANNEL NTERRUPT OURCE NTERRUPT OURCE controlled through 4 configuration registers [TIMERCNTL, TIMER, Bit-9 Bit-8 Bit-7 Bit-6 27 XR16M698 C NCODING AND LEARING C AND LEARING DEFAULT TIMERLSB Register Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 ...

Page 28

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO TIMERCNTL [7:4] Reserved TIMERCNTL [3:0] These bits are used to invoke a series of commands that control the function of the Timer/Counter. The commands 1011 to 1111 are reserved. 0001: Enable Timer Interrupt 0010: Disable Timer Interrupt (default) ...

Page 29

... Programmable Baud Rate Generator with Fractional Divisor” on page 9 Individual UART Channel 8X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch HOT AND E TRIGGERABLE ODES Timer Timed TIMERCNTL Out read 8XMODE Register Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 4XMODE Register Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 29 XR16M698 Timer Timed TIMERCNTL Timer Timed Out read Out ...

Page 30

... DVID register provides device identification. A return value of 0x68 from this register indicates the device is a XR16M698. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes ...

Page 31

... OMPATIBLE Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Write-only Read/Write E R NHANCED EGISTER Read/Write Read/Write Read-only Read-only Write-only Read-only Write-only Read-only Write-only Read-only Write-only Read-only 31 XR16M698 C OMMENTS LCR[ LCR[ LCR[ LCR[ LCR[ LCR[ Xon,Xoff Rcvd. Flags ...

Page 32

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO T 13: UART C C ABLE HANNEL DDRESS EG EAD A3- AME RITE RHR R Bit THR W Bit DLL R/W Bit DLM R/W Bit DLD ...

Page 33

... W Bit XON2 W Bit MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16M698. They are present for 16C550 compat- OTE Figure 11 ibility during Internal loopback, see 4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 Receive Holding Register (RHR) - Read Only SEE”RECEIVER” ON PAGE 13. . ...

Page 34

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from LOW to HIGH ...

Page 35

... Xon or Xoff character interrupt is cleared by a read to ISR register. • Special character interrupt is cleared by a read to ISR register or after the next character is received. • RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register. • Wake-up Indicator is cleared by a read to the INT0 register. 35 XR16M698 ...

Page 36

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled ...

Page 37

... Table 15 below shows the selections. R FIFO T T ECEIVE RIGGER ABLE AND FCR ECEIVE RIGGER RANSMIT - BIT EVEL RIGGER EVEL XR16M698 L S EVEL ELECTION C OMPATIBILITY 16C650A, 16L651 ...

Page 38

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL, DLM, DLD) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected. ...

Page 39

... MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and S W TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7,8 1 (default) 5 1-1/2 6,7,8 2 BIT-0 W ORD LENGTH 0 5 (default Figure XR16M698 ...

Page 40

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode) This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to set ’ ...

Page 41

... MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 41 XR16M698 ...

Page 42

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. ...

Page 43

... ELAY XR16M698 RANSMIT TO ECEIVE ATA IT S IME ...

Page 44

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO MSR[2]: Receiver Disable This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a logic 1, the receiver will operate in one of the following ways character is being received at the time of setting this bit, that character will be correctly received. No ■ ...

Page 45

... MSR 7:2 bits are saved to retain the user settings. After a reset, all these bits are set to a logic compatible with ST16C550 mode (default). • Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are enabled. Table 18 ). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 45 XR16M698 ...

Page 46

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO EFR[3:0]: Software Flow Control Select Combinations of software flow control can be selected by programming these bits, as shown in below. T ABLE EFR -3 EFR -2 EFR BIT BIT ...

Page 47

... If the last received control character was a xon character or characters (xon1, xon2), this bit will be set to a logic 1. This bit will clear after the read. XCHAR [0]: Xoff Detect Indicator If the last received control character was a xoff character or characters (xoff1, xoff2), this bit will be set to a logic 1. This bit will clear after the read. 47 XR16M698 ...

Page 48

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO REGISTERS DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a DLM DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TFCNT TFTRG RFCNT RFTRG XCHAR ...

Page 49

... MAX IN -0.3 0.3 -0.3 0.6 -0.3 1.4 VCC 1.8 VCC 2.4 -0.3 -0.2 -0.3 0.5 -0.3 1.4 VCC 1.8 VCC 2.0 0.4 0.4 2.4 1.8 1.4 - XR16M698 3.63V -0.5 to VCC+0. - -65 to +150 C 500 mW 3 NITS ONDITIONS MAX 0.6 V VCC V 0.7 V VCC V 0 6mA 3mA -6mA -3mA OH V -10 uA ...

Page 50

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA (-40 to +85 C for industrial grade package), Vcc is 1.62V to 3.63V Load where applicable S P YMBOL ARAMETER T ,T Clock Pulse Period Crystal Frequency OSC T External Clock Frequency ...

Page 51

... Delay From IOR# To Reset Interrupt RRI T Delay From Stop To Interrupt SI T Delay From IOW# To Reset Interrupt WRI T Reset Pulse RST Bclk Baud Clock 1.8V 1.8V 2.5V 2.5V 3. 16X data rate 51 XR16M698 3.3V U NITS ...

Page 52

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO F 16 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOR# T RDV D0-D7 A0-A7 Valid Address T AS CS# IOW# D0- EAD AND RITE IMING RDH T RDV Valid Data 16 Mode (Intel) Data Bus Read Timing ...

Page 53

... T T CSL ADH T CSD T RWH T RDH Valid Data 68 Mode (Motorola) Data Bus Read Timing Valid Address T T CSL ADH T CSD T RWH T WDH Valid Data 68 Mode (Motorola) Data Bus Write Timing 53 XR16M698 Valid Address Valid Data 68Read Valid Address Valid Data 68Write ...

Page 54

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO F 18 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ECEIVE NTERRUPT IMING RX Start D0:D7 Bit INT (Reading data out of RHR) ...

Page 55

... ODE S top Bit trigger level TX FIFO drops below trigger level 55 XR16M698 D0: D0: FIFO drops below RX Trigger Level T T RRI RR Last Data B yte Transm itted S ...

Page 56

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...

Page 57

... B e 1.95 mm Form INCHES MILLIMETERS MIN MAX MIN 0.102 0.134 2.60 0.002 0.014 0.05 0.100 0.120 2.55 0.009 0.015 0.22 0.005 0.009 0.13 0.931 0.951 23.65 0.783 0.791 19.90 0.695 0.715 17.65 0.547 0.555 13.90 0.0256 BSC 0.65 BSC 0.026 0.037 0.65 0 ° 7 ° 0 ° 57 XR16M698 α L MAX 3.40 0.35 3.05 0.38 0.23 24.15 20.10 18.15 14.10 0.95 7 ° ...

Page 58

... XR16M698 1.62V TO 3.63V HIGH PERFORMANCE OCTAL UART WITH 32-BYTE FIFO REVISION HISTORY R D EVISION ATE P1.0.0 May 2008 Preliminary Datasheet. 1.0.0 May 2008 Final Datasheet. Updated DC and AC Electrical Characteristics. D ESCRIPTION 58 REV. 1.0.0 ...

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