xr16l2750im Exar Corporation, xr16l2750im Datasheet
xr16l2750im
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xr16l2750im Summary of contents
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APRIL 2005 GENERAL DESCRIPTION 1 The XR16L2750 (2750 low voltage dual universal asynchronous receiver and transmitter (UART) with 5 Volt tolerant inputs. The device operates from 2.25 to 5.5 Volt supply range and is pin-to-pin compatible to ...
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... CSB RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# ORDERING INFORMATION P N ART UMBER XR16L2750CJ 44-Lead PLCC XR16L2750IJ 44-Lead PLCC XR16L2750CM 48-Lead TQFP XR16L2750IM 48-Lead TQFP XR16L2750 6 48-pin TQFP XR16L2750 12 44-pin PLCC ...
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REV. 1.2.1 PIN DESCRIPTIONS Pin Description 44-PLCC 48-TQFP N AME DATA BUS INTERFACE ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO Pin Description 44-PLCC 48-TQFP N AME RXRDYB TXA 13 7 RXA 11 5 RTSA CTSA DTRA DSRA# 41 ...
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REV. 1.2.1 Pin Description 44-PLCC 48-TQFP N AME RXB 10 4 RTSB CTSB DTRB DSRB CDB RIB OP2B XTAL1 ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 1.0 PRODUCT DESCRIPTION The XR16L2750 (2750) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration registers. ...
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REV. 1.2.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2750 data interface supports the Intel compatible ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO CSA 2.6 Channel A and B Internal Registers Each UART channel in the 2750 has a set of enhanced registers for control, monitoring and data loading and unloading. ...
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REV. 1.2.1 2.8 INTA and INTB Outputs The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup. Table 3 and 4 summarize the operating behavior for the transmitter and receiver. Also see through ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally ...
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REV. 1.2.1 sampling clock rate mode (EMSR bit-7=0) to double the operating data rate. When using a non-standard data rate crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation. divisor (decimal) = ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock (EMSR Bit-7) 2.11.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up ...
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REV. 1.2.1 2.12.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to ...
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REV. 1.2.1 F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2750 will ...
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REV. 1.2.1 transmitter automatically re-asserts RTS# (LOW) output prior to sending the data. The RS485 half-duplex direction control output can be inverted by enabling EMSR bit-3. 2.19 Infrared Mode The 2750 UART includes the infrared encoder and decoder compatible ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 2.20 Sleep Mode with Auto Wake-Up The 2750 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All ...
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REV. 1.2.1 2.21 Internal Loopback The 2750 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 13 ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2750 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting ...
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REV. 1.2 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR ...
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REV. 1.2.1 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits 2 and 3) status will reflect ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt. (default) • Logic 1 = Enable the software flow control, receive Xoff interrupt. ...
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REV. 1.2 ABLE P ISR R RIORITY EGISTER EVEL ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the transmit FIFO ...
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REV. 1.2.1 T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table 4.6 Line Control Register ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO LCR[4]: TX and RX Parity Select If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format. • Logic 0 ...
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REV. 1.2.1 MCR[1]: RTS# Output The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by EFR bit-6. If the modem interface is not used, this output may be used ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO LSR[2]: Receive Data Parity Error Tag • Logic parity error (default). • Logic 1 = Parity error. The receive character in RHR does not have correct parity information and ...
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REV. 1.2.1 MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = ...
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REV. 1.2.1 4.15 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00. 4.16 Trigger Level ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO FCTR[6]: Scratchpad Swap • Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. • Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select ...
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REV. 1.2.1 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR bit-4 can be ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM and DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They ...
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REV. 1.2.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA=0 ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER - Crystal Frequency CLK External Clock Low/High Time OSC External Clock Frequency ...
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REV. 1.2.1 AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Reset Pulse Width RST N Baud Rate Divisor Bclk Baud Clock F 14 IGURE ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO F 16 IGURE ATA US EAD IMING A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- IGURE ATA US RITE ...
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REV. 1.2 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO F 20 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading ...
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REV. 1.2 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* Data in TX FIFO TXRDY IOW# (Loading data into FIFO) ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...
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REV. 1.2.1 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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... Rev 1.2.1 Updated the Data Access Times (T EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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REV. 1.2.1 GENERAL DESCRIPTION................................................................................................. 1 A ............................................................................................................................................... 1 PPLICATIONS F ..................................................................................................................................................... 1 EATURES F 1. XR16L2750 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ......................................................................................................... ...
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XR16L2750 2.25V TO 5.5V DUART WITH 64-BYTE FIFO 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 23 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... ...