71m6543h-igtr/f Maxim Integrated Products, Inc., 71m6543h-igtr/f Datasheet
71m6543h-igtr/f
Related parts for 71m6543h-igtr/f
71m6543h-igtr/f Summary of contents
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... High processing and sampling rates combined with differential inputs offer a powerful metering platform for commercial and industrial meters with up to class 0.2 accuracy (71M6543H). A complete array of code development tools, demonstration code, and reference designs enable rapid development and certification of meters that meet all ANSI and IEC electricity metering standards worldwide ...
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Data Sheet 1 Introduction ................................................................................................................................. 10 2 Hardware Description .................................................................................................................. 11 2.1 Hardware Overview............................................................................................................... 11 2.2 Analog Front-End (AFE) ........................................................................................................ 12 2.2.1 Signal Input Pins ....................................................................................................... 13 2.2.2 Input Multiplexer ........................................................................................................ 14 2.2.3 Delay Compensation ................................................................................................. 19 2.2.4 ADC ...
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... Meter Calibration ................................................................................................................... 96 5 Firmware Interface ....................................................................................................................... 97 5.1 I/O RAM Map –Functional Order ........................................................................................... 97 5.2 I/O RAM Map – Alphabetical Order ..................................................................................... 103 5.3 Reading the Info Page (71M6543H only) ............................................................................. 117 5.4 CE Interface Description ..................................................................................................... 119 5.4.1 CE Program ............................................................................................................ 119 5.4.2 CE Data Format ...................................................................................................... 119 5.4.3 Constants ................................................................................................................ 119 5.4.4 Environment ............................................................................................................ 120 5.4.5 CE Calculations ....................................................................................................... 120 5.4.6 CE Front-End Data (Raw Data) ............................................................................... 121 5 ...
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Data Sheet 5.4.8 CE Transfer Variables ............................................................................................. 124 5.4.9 Pulse Generation..................................................................................................... 126 5.4.10 CE Calibration Parameters ...................................................................................... 129 5.4.11 CE Flow Diagrams .................................................................................................. 130 6 71M6543F/H Specifications ....................................................................................................... 132 6.1 Absolute Maximum Ratings ................................................................................................. 132 6.2 Recommended External Components ...
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Figures Figure 1: IC Functional Block Diagram ..................................................................................................... 9 Figure 2: AFE Block Diagram (Shunts: One-Local, Three-Remotes) ...................................................... 12 Figure 3. AFE Block Diagram (Four CTs) ............................................................................................... 13 Figure 4: States in a Multiplexer Frame (MUX_DIV[3: .................................................................. 17 ...
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Data Sheet Tables Table 1. Required CE Code and Settings for 1-Local / 3-Remotes ......................................................... 15 Table 2. Required CE Code and Settings for CT Sensors ...................................................................... 16 Table 3: Multiplexer and ADC Configuration Bits .................................................................................... 19 Table 4. ...
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Table 49: Data/Direction Registers for SEGDIO16 to SEGDIO31 ........................................................... 60 Table 50: Data/Direction Registers for SEGDIO32 to SEGDIO45 ........................................................... 61 Table 51: Data/Direction Registers for SEGDIO51 to SEGDIO55 ........................................................... 61 Table 52: LCD_VMODE Configurations .................................................................................................. 62 Table 53: LCD Configurations ...
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Data Sheet Table 99: Crystal Oscillator Performance Specifications ....................................................................... 138 Table 100: PLL Performance Specifications ......................................................................................... 138 Table 101: VLCD Generator Specifications .......................................................................................... 139 Table 102: 71M6543F/H VREF Performance Specifications ................................................................. 141 Table 103: ADC Converter Performance Specifications ....................................................................... ...
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IADC0 IADC1 IADC2 VBIAS MUX IADC3 and IADC4 PREAMP IADC5 IADC6 IADC7 VREF VADC8 (VA) VADC9 (VB) VADC10 (VC) MUX CROSS MUX CTRL CK32 RTCLK (32KHz) XIN Oscillator XOUT 32 KHz 4.9 MHz CK_4X CLOCK GEN CKMPU_2x MUX_SYNC CKCE < ...
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... Data Sheet 1 Introduction This data sheet covers the 71M6543F (0.5%) and 71M6543H (0.1%) 4th-generation Teridian polyphase energy measurement system-on-chips (SoCs). The term “71M6543F/H” is used when discussing a device feature or behavior that is applicable to both part numbers. The appropriate part number is indicated when a device feature or behavior is being discussed that applies only to a specific part number. This data sheet also covers details about the companion 71M6xx3 isolated current sensor device ...
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Hardware Description 2.1 Hardware Overview The Teridian 71M6543F/H single-chip energy meter integrates all primary functional blocks required to implement a solid-state electricity meter. Included on the chip are: • An analog front-end (AFE) featuring a 22-bit second-order sigma-delta ADC ...
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Data Sheet number of LCD segments and DIO pins can be implemented in software to accommodate various requirements. In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature compensation mechanism includes a temperature sensor and associated controls ...
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The 71M6543F/H AFE can also be directly interfaced to Current Transformers (CTs), as seen in In this case, all voltage and current channels are multiplexed into a single second-order sigma-delta ADC in the 71M6543F/H and the 71M6xx3 remote isolated sensors ...
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Data Sheet Pins IADC0-IADC1 can be programmed individually to be differential or single-ended as determined by the DIFF0_E (I/O RAM 0x210C[4]) control bit. However, for most applications, IADC0-IADC1 are configured as a differential input to work with a resistive ...
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Table 1. Required CE Code and Settings for 1-Local / 3-Remotes I/O RAM Mnemonic Location FIR_LEN[1:0] 210C[2:1] ADC_DIV PLL_FAST MUX_DIV[3:0] 2100[7:4] MUX0_SEL[3:0] 2105[3:0] MUX1_SEL[3:0] 2105[7:4] 2104[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] 2104[7:4] MUX4_SEL[3:0] 2103[3:0] 2103[7:4] MUX5_SEL[3:0] 2102[3:0] MUX6_SEL[3:0] MUX7_SEL[3:0] 2102[7:4] 2101[3:0] MUX8_SEL[3:0] MUX9_SEL[3:0] ...
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Data Sheet Table 2. Required CE Code and Settings for CT Sensors I/O RAM I/O RAM Mnemonic Location FIR_LEN[1:0] 210C[2:1] 2200[5] ADC_DIV PLL_FAST 2200[4] MUX_DIV[3:0] 2100[7:4] MUX0_SEL[3:0] 2105[3:0] MUX1_SEL[3:0] 2105[7:4] MUX2_SEL[3:0] 2104[3:0] MUX3_SEL[3:0] 2104[7:4] MUX4_SEL[3:0] 2103[3:0] MUX5_SEL[3:0] 2103[7:4] MUX6_SEL[3:0] ...
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Using settings for the I/O RAM Mnemonics listed in those required by the corresponding CE code being used may result in undesirable side effects and must not be selected by the MPU. Consult your local Teridian representative to obtain the ...
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Data Sheet Multiplexer advance, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are controlled by the internal MUX_CTRL circuit. Additionally, MUX_CTRL launches each pass of the CE through its ...
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Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0], MUXn_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 Table 3 summarizes the I/O ...
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Data Sheet The recommended ADC multiplexer sequence samples the current first, immediately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle Ф relative to the current. The delay compensation implemented in ...
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V inp V inn CROSS Figure 6: General Topology of a Chopped Amplifier It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS (an internal signal), in the A ...
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Data Sheet 2.2.8 71M6xx3 Isolated Sensor Interface 2.2.8.1 General Description Non-isolating sensors, such as shunt resistors, can be connected to the inputs of the 71M6543F/H via a combination of a pulse transformer and a 71M6xx3 IC (a top-level block ...
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Command RCMD[4:2] 000 Invalid 001 Command 1 010 Command 2 011 Reserved 100 Reserved 101 Invalid 110 Reserved 111 Reserved Notes: 1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 ...
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Data Sheet Table 6: I/O RAM Control Bits for Isolated Sensor RST Name Address Default SFR RCMD[4:0] FC[4:0] PERR_RD SFR FC[6] PERR_WR SFR FC[5] CHOPR[1:0] 2709[7:6] 00 TMUXR2[2:0] 270A[2:0] 000 TMUXR4[2:0] 270A[6:4] 000 TMUXR6[2:0] 2709[2:0] 000 2602[7:0] RMT_RD[15:8] RMT_RD[7:0] ...
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Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE calculations and processes include: • Multiplication of each current sample with its associated voltage sample to obtain ...
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Data Sheet 2.3.4 Meter Equations The 71M6543F/H provides hardware assistance to the CE in order to support various meter equations. This assistance is controlled through I/O RAM field EQU[2:0] (equation assist, I/O RAM 0x2106[7:5]). The Compute Engine (CE) firmware ...
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A common use of the zero-crossing pulses is to generate interrupts in order to drive real-time clock software in places where the mains frequency is sufficiently accurate and also to adjust for crystal aging. A common use ...
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Data Sheet The WPULSE and VPULSE pulse generator outputs are available on pins SEGDIO0/WPULSE and SEGDIO1/VPULSE, respectively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53 (see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details). CK32 ...
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VA IA 61.04 µs 61.04 µs CK32 (32768 Hz) MUX STATE Figure 10: Samples from Multiplexer Cycle (Frame) The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of ...
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Data Sheet 2.4 80515 MPU Core The 71M6543F/H include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle. Using a 4.9 MHz clock results in a processing throughput of 4.9 MIPS. The 80515 architecture eliminates ...
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The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX A,@DPTR instruction (PDATA, SFR 0xBF, provides the upper 8 ...
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Data Sheet An alternative data pointer is available in the form of the PDATA register (SFR 0xBF), sometimes referred to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction ...
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Generic 80515 Special Function Registers Table 12 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional descriptions of the registers can be found at the page numbers listed in the table. Table 12: ...
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Data Sheet Accumulator (ACC, A, SFR 0x E0): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC. B Register (SFR 0xF0): The ...
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SFR SFR Name Address All DIO ports on the chip are bi-directional. Each of them consists of a latch (SFR P0 to P3), an output driver and an input buffer, therefore the ...
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Data Sheet The MPU core power consumption can be significantly reduced by the proper use of Idle Mode. The amount of power saved depends on the percentage of time spent in Idle Mode. Since some interrupts may occur frequently, ...
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UART 0 Mode 0 N/A Start bit, 8 data bits, stop bit, variable Mode 1 baud rate (internal baud rate generator or timer 1) Start bit, 8 data bits, parity, stop bit, Mode 2 fixed baud rate 1/32 or 1/64 ...
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Data Sheet Bit Symbol The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, S0CON[3] TB80 depending on the function it performs (parity check, multiprocessor communication etc.) In Modes 2 and 3 it ...
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Table 22: Timers/Counters Mode Description M1 M0 Mode 0 0 Mode Mode Mode Mode 3 In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 ...
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Data Sheet Table 25: The TCON Register Bit Functions (SFR 0x88) Bit Symbol TCON[7] TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared ...
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The Timer/Counter control registers, TCON and T2CON (see • The interrupt request register, IRCON (see • The interrupt priority registers: IP0 and IP1 (see Table 26: The IEN0 Bit Functions (SFR 0xA8) Bit Symbol EAL = 0 disables all ...
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Data Sheet Table 30: The T2CON Bit Functions (SFR 0xC8) Bit Symbol – Not used. T2CON[7] T2CON[6] I3FR Polarity control for INT3 falling edge rising edge. Polarity control for INT2: T2CON[5] I2FR 0 = falling ...
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SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY, RTC_1SEC, RTC_1MIN, RTC_T, ...
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Data Sheet IP1(SFR 0xB9) (Table 36). If requests of the same priority level are received simultaneously, an internal polling sequence as shown in Table 37 Changing interrupt priorities while interrupts are enabled can easily cause software defects ...
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Interrupt Sources and Vectors Table 38 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag IE0 TF0 IE1 TF1 RI0/TI0 RI1/TI1 IEX2 IEX3 IEX4 IEX5 IEX6 v1.0 © 2008–2011 Teridian Semiconductor Corporation Table 37: Interrupt Polling ...
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Data Sheet ...
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On-Chip Resources 2.5.1 Physical Memory 2.5.1.1 Flash Memory The 71M6543F/H includes on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE RAM and I/O RAM. On ...
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Data Sheet The page erase sequence is: • Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]). • Write the pattern 0x55 to the FLSH_ERASE register (SFR 0x94). Program Security When enabled, the security feature limits the ICE to global ...
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MPU/CE RAM The 71M6543F/H includes static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The 5KB of static RAM are used for data storage by both MPU and CE and ...
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Data Sheet Derived Clock From OSC Crystal MCK Crystal/PLL CKCE MCK CKADC MCK CKMPU MCK CKICE MCK CKOPTMOD MCK CK32 MCK 2.5.4 Real-Time Clock (RTC) 2.5.4.1 RTC General Description The RTC is driven directly by the crystal oscillator and ...
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Name Location Rst 2504[6:0] 40 RTCA_ADJ[6:0] RTC_P[16:14] 289B[2:0] 289C[7:0] RTC_P[13:6] 289D[7:2] RTC_P[5:0] RTC_Q[1:0] 289D[1:0] RTC_RD 2890[6] RTC_WR 2890[7] RTC_FAIL 2890[4] RTC_SBSC[7:0] 2892[7:0] 2.5.4.3 RTC Rate Control The 71M6543F/H has two rate adjustment mechanisms: • The first rate adjustment mechanism is ...
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Data Sheet The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by ∆ ppm, RTC_P and RTC_Q are calculated using the following equation: 4 Conversely, the amount of ppm shift for a given value ...
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The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000, the nominal ...
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Data Sheet … 252 253 254 255 For proper operation, the MPU has to load the lookup table with values that reflect the crystal properties with respect to temperature, which is typically done once ...
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Unlike earlier generation Teridian SoCs, the 71M6543F/H does not use the ADC to read the temperature sensor. Instead, it uses a technique that is operational in SLP and LCD mode, as well as BRN and MSN modes. This means that ...
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Data Sheet Name Location TEMP_START 28B4[6] TEMP_PWR 28A0[6] TEMP_BSEL 28A0[7] TEMP_TEST[1:0] 2500[1:0] STEMP[10:3] 2881[7:0] STEMP[2:0] 2882[7:5] BSENSE[7:0] 2885[7:0] BCURR 2704[3] 2.5.6 71M6xx3 Temperature Sensor The 71M6xx3 includes an on-chip temperature sensor for determining the temperature of its bandgap reference. ...
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In BRN mode, TEMP_PWR = TEMP_BSEL use: VBAT ( orVBAT _ RTC In MSN mode, a 100 µA de-passivation load can be applied to the selected battery (i.e., selected by the TEMP_BSEL bit) by setting the BCURR (I/O RAM 0x2704[3]) ...
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Data Sheet Bit Banged Optical UART (Third UART) As shown in Figure 15, the 71M6543F/H can also be configured to drive the optical UART with a DIO signal in a bit banged configuration. When control bit OPT_BB (I/O RAM ...
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Table 47: Selectable Resources using the DIO_Rn[2:0] Bits Value in DIO_Rn[2: Note: Resources are selectable only on SEGDIO2 through SEGDIO11 and the PB pin. See Table When driving LEDs, relay coils etc., the DIO ...
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Data Sheet SEGDIO36/SPI_CSZ…SEGDIO39/SPI_CKI (4 pins) o SEGDIO51/OPT_TX, SEGDIO55/OPT_RX (2 pins) o Additionally, 5 LCD segment (SEG) pins are available. These pins can be categorized as follows: 3 SEG pins combined with the ICE interface (SEG48/E_RXTX, SEG49/E_TCLK, o SEG50/E_RST) 2 ...
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Table 50: Data/Direction Registers for SEGDIO32 to SEGDIO45 SEGDIO 32 Pin # 7 0 Configuration DIO LCD 32 SEG Data Register 32 DIO Data Register 32 Direction Register input output Table 51: ...
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Data Sheet LCD_VMODE[1:0] LCD_EXT LDAC_E LCD_BSTE Description Notes: 1. LCD_EXT, LDAC_E and LCD_BSTE are 71M6543F/H internal signals which are decoded from the LCD_VMODE[1:0] control field setting (I/O RAM 0x2401[7:6]). Each of ...
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A small amount of power can be saved by programming the LCD frequency to the lowest value that provides satisfactory LCD visibility over the required temperature range. Table 53 shows all I/O RAM registers that control the operation of the ...
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Data Sheet The LCD bias may be compensated for temperature using the LCD_DAC[4:0] field (I/O RAM 0x240D[4:0]). The bias may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in MSN mode and VBAT in BRN and ...
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For example, if LCD_MAP[46 then pin 93 (TMUX2OUT/SEG46) is configured as SEG46, and if LCD_MAP[46]=0, then pin 93 is configured as TMUX2OUT. The SEG pins with alternate ICE interface function (see pins 56-58 in alternate ICE interface function ...
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Data Sheet 2.5.11.2 Three-Wire (µ-Wire) EEPROM Interface with Single Data Pin A 500 kHz three-wire interface, using SDATA, SDCK, and a DIO pin for CS is available. The interface is selected by setting DIO_EEX[1:0] = 10. The EECTRL bits ...
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EECTRL Byte Written Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure 19: 3-wire Interface. Write Command, HiZ=1 EECTRL Byte Written READ SCLK (output) SDATA (input) SDATA output Z BUSY (bit) Figure 20: 3-wire Interface. ...
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Data Sheet 1) An external host reads data from CE locations to obtain metering information. This can be used in applications where the 71M6543F/H function as a smart front-end with preprocessing capability. Since the addresses are in 16-bit format, ...
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Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI SAFE mode was created. In SPI ...
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Data Sheet Name Location Rst SPI_STAT 2708[7:0] 0 SPI Flash Mode (SFM) In normal operation, the SPI slave interface cannot read or write the flash memory. However, the 71M6543F/H supports a special flash mode (SFM) which facilitates initial programming ...
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Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM. o 0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes o are blocked and the user ...
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Data Sheet One of the digital or analog signals listed in Table 61 can be selected to be output on the TMUXOUT pin. The function of the multiplexer is controlled with the I/O RAM register TMUX[4:0] (I/O RAM 0x2502[4:0], ...
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Signal Name TMUX2[4:0] 0 WD_OVF 1 PULSE_1S 2 PULSE_4S 3 RTCLK SPARE[1] bit – I/O RAM 8 0x2704[1] SPARE[2] bit – I/O RAM 9 0x2704[2] A WAKE B MUX_SYNC C MCK E GNDD 12 INT0 – DIG I/O 13 INT1 ...
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Data Sheet 3 Functional Description 3.1 Theory of Operation The energy delivered by a power source into a load can be expressed as: Assuming phase angles are constant, the following formulae apply: Real Energy [Wh] = ...
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When system power is not available, the 71M6543F one of three battery modes: • BRN mode (brownout mode) • LCD mode (LCD-only mode) • SLP mode (sleep mode). An internal comparator monitors the voltage at the V3P3SYS pin ...
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Data Sheet Transitions from both LCD and SLP mode to BRN mode can be initiated by the following events: • Wake-up timer timeout. • Pushbutton (PB) is activated. • A rising edge on SEGDIO4, SEGDIO52 or SEGDIO55. • Activity ...
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BRN Mode In BRN mode, most non-metering digital functions are active (as shown in EEPROM, LCD and RTC. In BRN mode, the PLL continues to function at the same frequency as MSN mode the MPU ...
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Data Sheet 3.2.3 SLP Mode The SLP mode may be commanded by the MPU whenever main system power is absent by asserting the SLEEP bit (I/O RAM 0x28B2[7]). The purpose of the SLP mode is to consume the least ...
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Fault and Reset Behavior 3.3.1 Events at Power-Down Power fault detection is performed by internal comparators that monitor the voltage at the V3P3A pin and also monitor the internally generated VDD pin voltage (2.5 VDC). The V3P3SYS and V3P3A ...
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Data Sheet 3.3.2 IC Behavior at Low Battery Voltage When system power is not present, the 71M6543F/H relies on the VBAT pin for power. If the VBAT voltage is not sufficient to maintain VDD at 2.0 VDC or greater, ...
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In normal operation, the WDT is reset by periodically writing a one to the WD_RST control bit I/O RAM 0x28B4[7]). The watchdog timer is also reset when the 71M6543F/H wakes from LCD or SLP mode, and when ICE_E=1. 3.4 Wake-Up ...
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Data Sheet Wake Enable Name Location Name Always Enabled WF_OVF Always Enabled WF_CSTART Always Enabled WF_BADVDD *This pin is sampled every 2 ms and must remain high for declared a valid high level. This pin ...
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Flag Timer expiration WF_TMR WF_PB PB pin high level WF_RX Either edge RX pin SEGDIO4 rising edge WF_DIO4 WF_DIO52 SEGDIO52 high level If OPT_RXDIS = 1 (I/O RAM 0x2457[2]), wake on SEGDIO55 high WF_DIO55 If OPT_RXDIS = 0 wake on ...
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Data Sheet active power (Wh), reactive power (VARh), A are then accessed by the MPU, processed further and output using the peripheral devices available to the MPU. Both the CE and multiplexer are controlled by the MPU via shared ...
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Application Information 4.1 Connecting 5 V Devices All digital input pins of the 71M6543F/H are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V ...
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... LOAD POWER SUPPLY NEUTRAL Note: This system is referenced to Neutral 3x TERIDIAN 71M6xx3 MUX and ADC V3P3A V3P3SYS IADC0 } IN* IADC1 VADC10 (VC) TERIDIAN IADC6 } IC IADC7 71M6543F/ VADC9 (VB) 71M6543H IADC4 } IB IADC5 VADC8 (VA) IADC2 } TEMPERATURE IA IADC3 SENSOR VREF RAM SERIAL PORTS COMPUTE TX ENGINE RX FLASH MEMORY MODUL- ...
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... Note: This system is referenced to Neutral POWER SUPPLY NEUTRAL MUX and ADC V3P3A V3P3SYS GNDA GNDD IADC2 } IA PWR MODE IADC3 VADC8 (VA) TERIDIAN IADC4 } IB 71M6543F/ IADC5 REGULATOR VADC9 (VB) 71M6543H IADC6 } IC IADC7 VBAT_RTC VADC10 (VC) IADC0 } TEMPERATURE IN* IADC1 SENSOR VREF RAM SERIAL PORTS COMPUTE TX ENGINE LCD DRIVER ...
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... Teridian implements a two step procedure to trim and characterize the VREF voltage reference during the device manufacturing process. The first step in the process is applied to both the 71M6543F and 71M6543H parts. In this first step, the reference voltage (VREF) is trimmed to a target value of 1.195V. During this trimming process, the TRIMT[7:0] (I/O RAM 0x2309) value is stored in non-volatile fuses ...
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... TRIMT[7:0] trims the VREF voltage for minimum variation with temperature. The TRIMT[7:0] fuses are read by the MPU directly at I/O RAM address 0x2309[7:0]. During the second pass trim for the 71M6543H, VREF is further characterized at 85°C and 22°C, and the resulting fuse trim values are stored in TRIMBGB[15:0] and TRIMBGD[7:0], respectively. TRIMBGB[15:0] and TRIMBGD[7:0] cannot be read directly by the MPU ...
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Data Sheet Referring to Figure 31, the VADC8 (VA), VADC9 (VB) and VADC10 (VC) voltage sensors are always directly connected to the 71M6543F/H. Thus, the precision of the voltage sensors is primarily affected by VREF in the 71M6543F/H. The ...
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... For the 71M6543H (±0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF behavior of each individual part across industrial temperatures (see The resulting tracking of the reference VREF voltage is within ± ...
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... These coefficients are designed to achieve ±40 ppm/°C for VREF. For the 71M6543H (±0.1% energy accuracy), coefficients specific to each individual device can be calculated from values read from additional on-chip fuses that characterize the VREF behavior of each individual part across industrial temperatures (see The resulting tracking of the reference VREF voltage is within ± ...
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Connecting I C EEPROMs EEPROMs or other I C compatible devices should be connected to the DIO pins SEGDIO2 and SEGDIO3, as shown in Figure 33. Pullup resistors of roughly 10 kΩ to V3P3D ...
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Data Sheet The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not available in BRN mode. The OPT_TXMOD bit (I/O RAM 0x2456[1]) enables modulation. The duty cycle is controlled by OPT_FDC[1:0] (I/O ...
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Connecting the Emulator Port Pins Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection from EMI as illustrated in Figure V3P3D 62 Ω 62 Ω 62 Ω Figure 37: ...
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Data Sheet 4.15 Meter Calibration Once the Teridian 71M6543F/H energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • Establishment of the reference temperature for factory calibration (e.g., ...
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Firmware Interface 5.1 I/O RAM Map –Functional Order In Table 69 and Table 70, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits are identified with a ‘U’. Unimplemented bits have no memory storage, writing ...
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Data Sheet Name Addr Bit 7 LCD_MAP6 2014 LCD_MAP5 2015 LCD_MAP4 2016 LCD_MAP3 2017 LCD_MAP2 2018 LCD_MAP1 2019 LCD_MAP0 201A DIO_R5 201B U DIO_R4 201C U DIO_R3 201D U DIO_R2 201E U DIO_R1 201F U DIO_R0 2020 U DIO0 ...
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Table 70 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits have a darker gray background. Name Addr Bit 7 Bit 6 CE and ADC MUX5 ...
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Data Sheet Name Addr Bit 7 Bit 6 LCD_MAP2 2409 LCD_MAP1 240A LCD_MAP0 240B LCD4 240C U LCD_DAC 240D U SEGDIO0 2410 U … … U SEGDIO15 241F U SEGDIO16 2420 U … … U SEGDIO45 243D U SEGDIO46 ...
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Name Addr Bit 7 Bit 6 REMOTE2 2602 REMOTE1 2603 RBITS INT1_E 2700 EX_EEX EX_XPULSE INT2_E 2701 EX_SPI EX_WPULSE SECURE 2702 FLSH_UNLOCK[3:0] Analog0 2704 VREF_CAL VREF_DIS VERSION 2706 INTBITS 2707 U INT6 FLAG0 SFR E8 IE_EEX IE_XPULSE FLAG1 SFR F8 ...
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Data Sheet Name Addr Bit 7 Bit 6 RTC5 2895 U RTC6 2896 U RTC7 2897 U RTC8 2898 U RTC9 2899 RTC10 289B U RTC11 289C RTC12 289D RTC13 289E U RTC14 289F U TEMP 28A0 TEMP_BSEL TEMP_PWR ...
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I/O RAM Map – Alphabetical Order Table 71 lists I/O RAM bits and registers in alphabetical order. Bits with a write direction (W in column Dir) are written by the MPU into configuration RAM. Typically, they are initially stored ...
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Data Sheet Name Location Rst Wk Dir CHOPR[1:0] 2709[7: R/W DIFF0_E 210C[4] 0 DIFF2_E 210C[5] 0 DIFF4_E 210C[6] 0 DIFF6_E 210C[7] 0 2455[2:0] DIO_R2[2:0] 0 DIO_R3[2:0] 2455[6:4] 0 2454[2:0] DIO_R4[2:0] 0 2454[6:4] 0 DIO_R5[2:0] DIO_R6[2:0] 2453[2:0] 0 ...
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Name Location Rst Wk Dir DIO_EEX[1:0] 2456[7:6] 0 2457[6] 0 DIO_PV DIO_PW 2457[7] 0 DIO_PX 2458[7] 0 DIO_PY 2458[6] 0 EEDATA[7:0] SFR 9E 0 EECTRL[7:0] SFR 9F 0 2106[7:5] 0 EQU[2:0] v1.0 Description When set, converts SEGDIO3 and SEGDIO2 to ...
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Data Sheet Name Location Rst Wk Dir 2700[0] EX_XFER EX_RTC1S 2700[1] EX_RTC1M 2700[2] EX_RTCT 2700[3] EX_SPI 2701[7] 0 EX_EEX 2700[7] EX_XPULSE 2700[6] EX_YPULSE 2700[5] EX_WPULSE 2701[6] EX_VPULSE 2701[5] EW_DIO4 28B3[2] 0 EW_DIO52 28B3[1] 0 EW_DIO55 28B3[0] 0 EW_PB 28B3[3] ...
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Name Location Rst Wk Dir FLSH_ERASE[7:0] SFR 94[7:0] 0 FLSH_MEEN SFR B2[1] 0 FLSH_PEND SFR B2[3] 0 FLSH_PGADR[5:0] SFR B7[7:2] 0 FLSH_PSTWR SFR B2[2] 0 FLSH_PWE SFR B2[0] 0 FLSH_RDE 2702[2] – FLSH_UNLOCK[3:0] 2702[7:4] 0 FLSH_WRE 2702[1] – v1.0 Description ...
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Data Sheet Name Location Rst Wk Dir IE_XFER SFR E8[0] IE_RTC1S SFR E8[1] SFR E8[2] IE_RTC1M IE_RTCT SFR E8[3] IE_SPI SFR F8[7] 0 IE_EEX SFR E8[7] IE_XPULSE SFR E8[6] IE_YPULSE SFR E8[5] IE_WPULSE SFR F8[4] IE_VPULSE SFR F8[3] INTBITS ...
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Name Location Rst Wk Dir 2405[7:0] 0 LCD_MAP[55:48] LCD_MAP[47:40] 2406[7:0] 0 LCD_MAP[39:32] 2407[7:0] 0 LCD_MAP[31:24] 2408[7:0] 0 LCD_MAP[23:16] 2409[7:0] 0 LCD_MAP[15:8] 240A[7:0] 0 LCD_MAP[7:0] 240B[7:0] 0 LCD_MODE[2:0] 2400[6:4] 0 LCD_ON 240C[0] 0 LCD_BLANK 240C[1] 0 LCD_ONLY 28B2[6] 0 LCD_RST 240C[2] ...
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Data Sheet Name Location Rst Wk Dir LCD_VMODE[1:0] 2401[7: R/W LCD_Y 2400[2] 0 LKPADDR[6:0] 2887[6:0] 0 2887[7] 0 LKPAUTOI 2888[7:0] 0 LKPDAT[7:0] LKP_RD 2889[1] 0 LKP_WR 2889[0] 0 MPU_DIV[2:0] 2200[2:0] 0 2105[3:0] 0 MUX0_SEL[3:0] MUX1_SEL[3:0] 2105[7:4] 0 ...
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Name Location Rst Wk Dir OPT_BB 2457[0] 0 OPT_FDC[1:0] 2457[5:4] 0 OPT_RXDIS 2457[2] 0 OPT_RXINV 2457[1] 0 OPT_TXE [1,0] 2456[3:2] 00 – OPT_TXINV 2456[0] 0 OPT_TXMOD 2456[1] 0 OSC_COMP 28A0[5] 0 PB_STATE SFR F8[0] 0 PERR_RD SFR FC[6] 0 PERR_WR ...
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Data Sheet Name Location Rst Wk Dir PLS_MAXWIDTH[7:0] 210A[7: R/W PLS_INTERVAL[7:0] 210B[7:0] 0 PLS_INV 210C[0] 0 PORT_E 270C[5] 0 PRE_E 2704[5] 0 PREBOOT SFRB2[7] – RCMD[4:0] SFR FC[4:0] 0 RESET 2200[3] 0 RFLY_DIS 210C[3] 0 RMT2_E 2709[3] ...
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Name Location Rst Wk Dir 2504[6:0] 40 – RTCA_ADJ[6:0] RTC_FAIL 2890[4] 0 RTC_P[16:14] 289B[2:0] 4 RTC_P[13:6] 289C[7:0] 0 RTC_P[5:0] 289D[7:2] 0 RTC_Q[1:0] 289D[1:0] 0 RTC_RD 2890[6] 0 RTC_SBSC[7:0] 2892[7:0] – 289E[5:0] 0 RTC_TMIN[5:0] 289F[4:0] 0 RTC_THR[4:0] RTC_WR 2890[7] 0 RTC_SEC[5:0] ...
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Data Sheet Name Location Rst Wk Dir SFR B2[6] 0 SECURE SLEEP 28B2[7] 0 SPI_CMD SFR FD[7:0] – SPI_E 270C[4] 1 SPI_SAFE 270C[3] 0 SPI_STAT 2708[7:0] 0 2881[7:0] – STEMP[10:3] STEMP[2:0] 2882[7:5] – SUM_SAMPS[12:8] 2107[4:0] 0 2108[7:0] SUM_SAMPS[7:0] 28A0[3] ...
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Name Location Rst Wk Dir TEMP_PWR 28A0[6] 0 28B4[6] 0 TEMP_START 2502[5:0] – TMUX[5:0] TMUX2[4:0] 2503[4:0] – TMUXR2[2:0] 270A[2:0] TMUXR4[2:0] 270A[6:4] 000 000 R/W TMUXR6[2:0] 2709[2:0] VERSION[7:0] 2706[7:0] – VREF_CAL 2704[7] 0 VREF_DIS 2704[6] 0 VSTAT[2:0] SFR F9[2:0] – v1.0 ...
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Data Sheet Name Location Rst Wk Dir 28B2[5] 0 WAKE_ARM WAKE_TMR 2880[7:0] 0 WD_RST 28B4[7] 0 WF_DIO4 28B1[2] 0 WF_DIO52 28B1[1] 0 WF_DIO55 28B1[0] 0 WF_TMR 28B1[5] 0 WF_PB 28B1[3] 0 WF_RX 28B1[4] 0 WF_CSTART 28B0[7] 0 WF_RST 28B0[6] ...
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... Reading the Info Page (71M6543H only) High precision trim fuse values provided in the 71M6543H device cannot be directly accessed through the I/O RAM space. These trim fuses reside in a special area termed the “Info Page”. The MPU gains access to the Info Page by setting the INFO_PG (I/O RAM 0x270B[0]) control bit. Once the INFO_PG bit is set, Info Page contents are accessible in program memory space based at the address specified by the contents of CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) ...
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Data Sheet Page data objects are 2’s complement format and should be sign extended when read into a 16-bit data type (see case _TEMP85 in the code example). #if HIGH_PRECISION_METER int16_t read_trim (enum eTRIMSEL select) { uint8r_t *px; int16_t ...
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CE Interface Description 5.4.1 CE Program The CE performs the precision computations necessary to accurately measure power. These computations include offset cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag detection and voltage phase measurement. All ...
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Data Sheet 5.4.4 Environment Before starting the CE using the CE_E bit (I/O RAM 0x2106[0]), the MPU has to establish the proper environment for the CE by implementing the following steps: • Locate the CE code in Flash memory ...
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CE Front-End Data (Raw Data) Access to the raw data provided by the AFE is possible by reading CE RAM addresses 0 through A, as shown in Table 74. In the expression MUXn_SEL[3: ‘n’ refers to the ...
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Data Sheet 5.4.7 CE Status and Control The CE Status Word is useful for generating early warnings to the MPU for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency. ...
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Table 78: CECONFIG Bit Definitions (CE RAM 0x20) CECONFIG Name Default bit 23 Reserved 22 EXT_TEMP 21 EDGE_INT 20 SAG_INT 19:8 SAG_CNT (0xDA) 7:6 FREQSEL[1:0] 5 EXT_PULSE 4:2 Reserved 1 PULSE_FAST 0 PULSE_SLOW The FREQSEL[1:0] field in CECONFIG (CE RAM ...
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Data Sheet The CE pulse generator can be controlled by either the MPU (external (internal) variables. Control is by the MPU if the EXT_PULSE bit = 1 (CE RAM 0x20[5]). In this case, the MPU controls the ...
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Table 81: CE Transfer Variables (with CTs) CE Name Address 0x84 WSUM_X The signed sum: W0SUM_X+W1SUM_X+W2SUM_X. 0x85 W0SUM_X The sum of Wh samples from each wattmeter 0x86 element. W1SUM_X 0x87 W2SUM_X 0x88 VARSUM_X The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X. 0x89 VAR0SUM_X The ...
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Data Sheet The RMS values can be computed by the MPU from the squared current and voltage samples as follows: ⋅ ⋅ IxSQSUM LSB 3600 = I Ix RMS N ACC Other transfer variables include those available for frequency ...
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APULSEW and APULSER to generate pulses. Irrespective of the EXT_PULSE status, the output pulse rate controlled by APULSEW and APULSER is implemented by the CE only. By setting EXT_PULSE = 1, the MPU is ...
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Data Sheet Table 86: CE Parameters for Noise Suppression and Code Version CE Name Default Address 0x26 QUANT_IA 0x27 QUANT_WA 0x28 QUANT_VARA 0x2A QUANT_IB 0x2B QUANT_WB 0x2C QUANT_VARB 0x2E QUANT_IC 0x2F QUANT_WC 0x30 QUANT_VARC 0x31 QUANT_ID LSB weights for ...
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CE Calibration Parameters Table 87 lists the parameters that are typically entered to effect calibration of meter accuracy. CE Defau Name Address lt 0x10 CAL_IA 16384 0x11 CAL_VA 16384 0x13 CAL_IB 16384 0x14 16384 CAL_VB 0x16 CAL_IC 16384 0x17 ...
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Data Sheet 5.4.11 CE Flow Diagrams Figure 39 through Figure 41 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations. multiplexer IA VA ...
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VARA VARB VARC SQUARE Figure 41: CE Data Flow: Squaring and Summation Stages v1.0 © 2008–2011 Teridian Semiconductor Corporation SUM Σ Σ SUM_SAMPS = 2184 IASQ SUM IBSQ ...
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Data Sheet 6 71M6543F/H Specifications This section provides the electrical specifications for the 71M6543F/H. Please refer to the 71M6xxx Data Sheet for the 71M6xx3 electrical specifications, pin-out and package mechanical data. 6.1 Absolute Maximum Ratings Table 88 shows the ...
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Recommended External Components Table 89: Recommended External Components Name From To C1 V3P3A GNDA C2 V3P3D GNDD CSYS V3P3SYS GNDD CVDD VDD GNDD CVLCD VLCD GNDD XTAL XIN XOUT CXS XIN GNDA CXL XOUT GNDA 6.3 Recommended Operating Conditions ...
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Data Sheet 6.4 Performance Specifications 6.4.1 Input Logic Levels Parameter 1 Digital high-level input voltage 1 Digital low-level input voltage , V Input pullup current E_RXTX, E_RST, E_TCLK OPT_RX, OPT_TX SPI_CSZ (SEGDIO36) Other digital inputs Input pull ...
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Battery Monitor Table 93: Battery Monitor Performance Specifications (TEMP_BAT = 1) Parameter BV: Battery Voltage (definition) Measurement Error BV ⋅ − 100 1 VBAT Input impedance in continuous measurement, MSN mode. V(VBAT_RTC)/I(VBAT_RTC) Load ...
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Data Sheet 6.4.5 Supply Current Table 95: Supply Current Performance Specifications Parameter Condition Polyphase: 4 Currents, 3 Voltages V3P3A = V3P3SYS = 3.3 V, MPU_DIV [2:0]= 3 (614 kHz MPU clock), I1: V3P3A + V3P3SYS current, No Flash memory ...
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V3P3D Switch Table 96: V3P3D Switch Performance Specifications Parameter On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D V3P3D I , MSN OH V3P3D I , BRN OH 6.4.7 Internal Power Fault Comparators Parameter Overall response ...
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Data Sheet 6.4.9 2.5 V Voltage Regulator – Battery Power Table 98: Low-Power Voltage Regulator Performance Specifications Parameter V2P5 V2P5 load regulation Voltage Overhead 2V − VBAT-VDD 6.4.10 Crystal Oscillator Table 99: Crystal Oscillator Performance Specifications Parameter Maximum Output ...
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VLCD Generator Table 101: VLCD Generator Specifications Parameter VSYS to VLCD switch impedance VBAT to VLCD switch impedance LCD Boost Frequency VLCD IOH current (VLCD(0)-VLCD(IOH)<0.25) ������������ ( ������_������ 5���� �������������0 + From LCDADJ0 and LCDADJ12 fuses: ( ...
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Data Sheet Parameter LCD_DAC Error. VLCD-VLCDnom Zero Scale, no Boost V3P3 = 3.6 V V3P3 = 3.0 V VBAT = 4.0 V, V3P3 = 0 V, BRN Mode VBAT = 2.5 V, V3P3 = 0 V, BRN Mode LCD_DAC ...
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... VREF output voltage, VREF(22) VREF chop step, trimmed VREF power supply sensitivity ΔVREF / ΔV3P3A VREF input impedance VREF output impedance VNOM definition (see note 2) If temperature characterization trim information is available (71M6543H, 0.1%) VNOM temperature coefficients: TC1 = TC2 = VREF(T) deviation from VNOM(T) (see note 1): − ...
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Data Sheet 6.4.15 ADC Converter Table 103: ADC Converter Performance Specifications Parameter Recommended Input Range (Vin - V3P3A) Voltage to Current Crosstalk Vcrosstalk ∠ − ∠ cos( Vin Vcrosstalk Vin (see note 1) Input Impedance, no ...
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Parameter Note: 1. Guaranteed by design; not production tested. 2. Unless stated otherwise, the following test conditions apply to all the parameters provided in this table: FIR_LEN[1:0]=1, VREF_DIS=0, PLL_FAST=1, ADC_DIV=0, LSB values do not include the 9-bit left shift at ...
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Data Sheet 6.5 Timing Specifications 6.5.1 Flash Memory Table 105: Flash Memory Timing Specifications Parameter Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page Erase ...
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RESET Pin Parameter Reset pulse width Reset pulse fall time (see note 1) Note: 1. Guaranteed by design; not production tested. 6.5.5 Real-Time Clock (RTC) Parameter Range for date v1.0 © 2008–2011 Teridian Semiconductor Corporation Table 108: RESET Pin ...
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Data Sheet 6.6 Typical Performance Data 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.1 Figure 42: Wh Error from 200 Hz, 240 VAC 1 0.8 0.6 0.4 0.2 0 ...
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Figure 44: Wh Error from 200 Various Frequencies (0° Load angle, 240 VAC) v1.0 © 2008–2011 Teridian Semiconductor Corporation 1 10 Current (Amperes) ...
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Data Sheet 6.7 100-Pin LQFP Package Outline Drawing Controlling dimensions are in mm. 1 14.000 +/- 0.200 0.225 +/- 0.045 Figure 45: 100-pin LQFP Package Outline 148 © 2008–2011 Teridian Semiconductor Corporation 15.7(0.618) 16.3(0.641) Top View MAX. 1.600 1.50 ...
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Pinout 1 SPI_DI/SEGDIO38 2 SPI_DO/SEGDIO37 SPI_CSZ/SEGDIO36 3 SEGDIO35 4 SEGDIO34 5 SEGDIO33 6 SEGDIO32 7 SEGDIO31 8 SEGDIO30 9 SEGDIO29 10 SEGDIO28 11 COM0 12 COM1 13 COM2 14 COM3 15 SEGDIO27/COM4 16 SEGDIO26/COM5 17 SEGDIO25 18 SEGDIO24 ...
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Data Sheet 6.9 71M6543F/H Pin Descriptions 6.9.1 71M6543F/H Power and Ground Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified under Section Table 110: ...
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Analog Pins Pin types Power Output Input, I/O = Input/Output. The circuit number denotes the equivalent circuit, as specified in Section 6.9.4. Pin Name Type 87 IADC0 86 IADC1 68 IADC2 67 ...
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Data Sheet 6.9.3 71M6543F/H Digital Pins Pin types Power Output Input, I/O = Input/Output, N connect. The circuit number denotes the equivalent circuit, as specified in Section 6.9.4. Pin Name 12–15 ...
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Pin Name 91 RESET TEST 90 PB 26, 40, 48, 49, 50, 73, NC 74, 77, 78, 79 v1.0 © 2008–2011 Teridian Semiconductor Corporation Type Circuit Chip Reset. This input pin is used to reset ...
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Data Sheet 6.9.4 I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin ...
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... Teridian Semiconductor Corporation Table 113. 71M6543F/H Ordering Guide Flash Size Packaging (KB) 64 bulk 64 tape and reel 71M6543F-IGTR/F 64 bulk 64 tape and reel 71M6543F/H Data Sheet Package Order Number Marking 71M6543F-IGT/F 71M6543F-IGT 71M6543F-IGT 71M6543H-IGT/F 71M6543H-IGT 71M6543H-IGTR/F 71M6543H-IGT (page 88). 155 ...
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Data Sheet Appendix A: Acronyms AFE Analog Front-End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit ...
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Appendix B: Revision History REVISION REVISION NUMBER DATE 1.0 1/11 Initial release Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right ...