71m6513h-igt Maxim Integrated Products, Inc., 71m6513h-igt Datasheet

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71m6513h-igt

Manufacturer Part Number
71m6513h-igt
Description
3-phase Energy Meter Ic
Manufacturer
Maxim Integrated Products, Inc.
Datasheet

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GENERAL DESCRIPTION
The TERIDIAN 71M6513 is a highly integrated SOC with an MPU core,
RTC, FLASH and LCD driver. TERIDIAN’s patented Single Converter
Technology™ with a 21-bit delta-sigma ADC, 6 analog inputs, digital tem-
perature compensation, precision voltage reference and 32-bit computation
engine (CE) supports a wide range of poly-phase metering applications with
very few low cost external components. A 32kHz crystal time base for the
entire system and internal battery backup support for RAM and RTC further
reduce system cost.
Maximum design flexibility is supported with multiple UARTs, I
fail comparator, a 5V LCD charge pump, up to 22 DIO pins and an in-
system programmable FLASH. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction residential/commercial
meter applications requiring multiple voltage/current inputs and complex
LCD or DIO configurations.
A complete array of ICE and development tools, programming libraries and
reference designs enable rapid development and certification of meters that
meet most demanding worldwide electricity metering standards.
Page: 1 of 96
NEUTRAL
LIVE
LIVE
LIVE
CT /COIL
POWER
FAULT
AMR
Etc.
IR
SERIAL PORTS
COMPARATOR
VOLTAGE REF
SENSE
TX
DRIVE
CONVERTER
RX
V A
VB
VC
IA
IB
IC
VBIAS
V1
V2
V3
VREF
RX
TX
TEMP SENSOR
TERIDIAN
71M6513
COMPUTE
ENGINE
TIMERS
FLASH
V3.3A V3.3D
MPU
RAM
RTC
ICE
POWER SUPPLY
© 2005-2008 TERIDIAN Semiconductor Corporation
LOAD
GNDA GNDD
REGULATOR
LCD DRIVER
SEG 24..27
SEG 32..41
DIO, PULSE
DIO 12..21
5V BOOST
SEG0..23
OSC/PLL
DIO 0..11
COM0..3
VDRV
VLCD
VBAT
XOUT
V2.5
XIN
88.88.8888
EEPROM
32 kHz
2
C, a power
BATTERY
3/5V LCD
MISC
3-Phase Energy Meter IC
71M6513/71M6513H
DATA SHEET
Wh accuracy over temperature and
Exceeds IEC62053 / ANSIC12.20.
Voltage reference
Six sensor inputs - VDD referenced
Auxiliary analog input for neutral
Low jitter Wh/VARh pulse outputs
Pulse count for pulse outputs
Four-quadrant metering
Phase sequencing
Line frequency count for RTC
Digital temperature compensation
Sag detection
Independent 32-bit compute engine
40-70Hz line frequency range with
Phase compensation (±7°)
Battery Backup for RAM and RTC
22mW @3.3V, 7.2μW back up
Flash memory option with security
8-bit MPU (80515) - 1 clock cycle per
instruction
LCD driver (≤168 pixels)
High speed SSI serial output
RTC for time-of-use functions
Hardware watchdog timer
Up to 22 general-purpose I/O pins
64KB Flash, 7KB RAM
Two UARTs for IR and AMR
100-pin LQFP package
2000:1 range
< 0.1% -- 71M6513H,
< 0.5% -- 71M6513
< 10ppm/°C -- 71M6513H,
< 50ppm/°C -- 71M6513
current
same calibration
FEATURES
AUGUST 2008
V2.5

Related parts for 71m6513h-igt

71m6513h-igt Summary of contents

Page 1

... FEATURES Wh accuracy over temperature and 2000:1 range < 0.1% -- 71M6513H, < 0.5% -- 71M6513 Exceeds IEC62053 / ANSIC12.20. Voltage reference < 10ppm/°C -- 71M6513H, < 50ppm/°C -- 71M6513 Six sensor inputs - VDD referenced Auxiliary analog input for neutral current Low jitter Wh/VARh pulse outputs Pulse count for pulse outputs ...

Page 2

... Real-Time Clock (RTC) ................................................................................................................... 38 Comparators (V2, V3) ...................................................................................................................... 38 LCD Drivers ..................................................................................................................................... 39 LCD Voltage Boost Circuitry ............................................................................................................ 39 UART (UART0) and Optical Port (UART1) ...................................................................................... 40 Hardware Reset Mechanisms .......................................................................................................... 40 Reset Pin (RESETZ) ....................................................................................................................... 40 Hardware Watchdog Timer .............................................................................................................. 40 Page 3-Phase Energy Meter IC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 3

... VARh Accuracy at Room Temperature .......................................................................................................... 73 Harmonic Performance .................................................................................................................................. 74 Meter Accuracy over Temperature (71M6513H) ............................................................................................ 74 APPLICATION INFORMATION ................................................................................................................................... 75 Connection of Sensors (CT, Resistive Shunt, Rogowski Coil) ....................................................................... 75 Distinction between 71M6513 and 71M6513H Parts ..................................................................................... 75 Temperature Compensation and Mains Frequency Stabilization for the RTC ............................................... 76 External Temperature Compensation ............................................................................................................ 77 Temperature Measurement ........................................................................................................................... 77 Connecting LCDs ........................................................................................................................................... 78 Connecting I2C EEPROMs ...

Page 4

... Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................ 49 Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up .............................. 50 Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................... 52 Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................. 52 Page 3-Phase Energy Meter IC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 5

... Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping ......................................... 53 Figure 24: Wh Accuracy, 0.3A - 200A/240V .................................................................................................. 73 Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................... 73 Figure 26: 71M6513H Wh Accuracy over Current at Various Temperatures ................................................. 73 Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................. 74 Figure 28: Typical Meter Accuracy over Temperature Relative to 25°C (w/ Temperature Compensation) ...

Page 6

... Table 55: Liquid Crystal Display Segment Table (Typical) ............................................................................. 39 Table 56: EECTRL Status Bits ....................................................................................................................... 42 Table 57: TMUX[3:0] Selections .................................................................................................................... 43 Table 58: SSI Pin Assignment ....................................................................................................................... 44 Table 59: Power Saving Measures ................................................................................................................ 50 Table 60: CHOP_EN Bits ............................................................................................................................... 51 Table 61: Frequency over Temperature ......................................................................................................... 76 Page 3-Phase Energy Meter IC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 7

... MPU (80515) 0000-07FF PROG FLASH 0000-FFFF (64KB) EERDSLOW EEWRSLOW EMULATOR V3P3 PORT RESETZ Figure 1: IC Functional Block Diagram © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V3P3A GNDA GNDA VOLTAGE BOOST VDRV LCD_IBST LCD_BSTEN GNDD GNDD VOLT REG V3P3D ...

Page 8

... VA, VB, and VC are typically connected to voltage sensors through resistor dividers. Page 3-Phase Energy Meter IC Hardware Overview Analog Front End (AFE) Alternate multiplexer sequence Mux State TEMP VA © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 9

... Voltage Reference The 71M6513/6513H includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference of the 71M6513H is trimmed in production to minimize errors caused by component mismatch and drift. The result is a voltage output with a predictable temperature coefficient. The voltage reference is chopper stabilized, i.e. the polarity can be switched by the MPU using the I/O RAM register CHOP_ENA (0x2002[5:4]). The two bits in the CHOP_ENA register enable the MPU to operate the chopper circuit in regular or inverted operation “ ...

Page 10

... MUX_ALT MUX_DIV Page 3-Phase Energy Meter IC VREF VBIAS VBIAS MUX (1.5V) V3P3A VREF CHOP_EN MUX VREF_DIS MUX CTRL CK32 Figure 3: AFE Block Diagram © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 ΔΣ ADC CONVERTER - FIR + FILTER VREF FIR_LEN V2.5 ...

Page 11

... IC V3P3 0x05 VC V3P3 0x06 TEMP VBIAS 0x07 V3 VBIAS Table 2: CE DRAM Locations for ADC Results © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET Description Phase A current Phase A voltage Phase B current Phase B voltage Phase C current Phase C voltage Temperature V3 monitor AUGUST 2008 V2.5 ...

Page 12

... © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Inputs used from alternate MUX sequence Mux State TEMP TEMP TEMP ...

Page 13

... 13/32768Hz = 397µs 13/32768Hz = 397µs per mux cycle per mux cycle Figure 4: Samples in Multiplexer Cycle 833ms 833ms Figure 5: Accumulation Interval © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 2/32768Hz = 2/32768Hz = 61.04µs 61.04µ XFER_BUSY XFER_BUSY ...

Page 14

... I/O RAM 0x2000 0x1FFF --- 0x1400 0x13FF CE DRAM 0x1000 0x0FFF --- 0x0800 0x07FF XRAM 0x0000 External data memory Figure 6: Memory Map © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 0xFF SFRs, RAM, reg. banks 0x00 Internal data memory V2.5 ...

Page 15

... Table 4: Stretch Memory Cycle Width © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Write signal width memrd memaddr memwr ...

Page 16

... S0RELL DIR0 IEN2 S1CON S1BUF DPS ERASE TL0 TL1 TH0 DPL DPH DPL1 Table 6: Special Function Registers Locations © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET Indirect addressing RAM Bin/Hex X101 X110 X111 USR2 PGADR S1RELL EEDATA EECTRL TH1 CKCON DPH1 ...

Page 17

... Serial Port 1, Reload Register, high byte User 2 Port, high address byte for MOVX@Ri Interrupt Request Control Register Program Status Word Baud Rate Control Register (only WDCON.7 bit used) Accumulator B Register Table 7: Special Function Registers Reset Values © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 18

... Table 8: PSW Register Flags RS1/RS0 Bank selected 00 Bank 0 01 Bank 1 10 Bank 2 11 Bank 3 Table 9: PSW bit functions © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB - P Location (0x00 – 0x07) (0x08 – 0x0F) (0x10 – 0x17) (0x18 – 0x1F) V2.5 ...

Page 19

... EEPROM, it places the data in EEDATA and then writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates the transmit sequence. See the section I2C Interface (EEPROM) for a description of the command and status bits available for EECTRL. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 20

... Interrupt inputs. The MPU may read these bits to see the input to external interrupts INT0, INT1 INT6. These bits do not have any memory and are primarily intended for debug use Table 11: Special Function Registers © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 21

... Start bit, 8 data bits, stop bit, variable baud rate CKMPU Table 13: UART Modes SM20 REN0 TB80 RB80 Table 14: The S0CON Register © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Using Internal Baud Rate Generator smod /( -S0REL)) ...

Page 22

... Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software. Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software Table 16: The S0CON Bit Functions © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET LSB TI1 RI1 SM0 ...

Page 23

... Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software Table 17: The S1CON Bit Functions M1 M0 GATE C/T Table 18: The TMOD Register © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET Baud Rate variable variable LSB M1 M0 Timer 0 AUGUST 2008 ...

Page 24

... If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. Table 20: Timers/Counters Mode Description TF0 TR0 IE1 IT1 Table 21: The TCON Register © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB IE0 IT0 V2.5 ...

Page 25

... Energy Meter IC Table 22: The TCON Register Bit Functions Timer 1 Mode 0 Mode 1 YES YES YES YES Not allowed Not allowed Table 23: Timer Modes Table 24: The PCON Register © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Mode 2 YES YES YES LSB V2.5 ...

Page 26

... EX1 Table 25: The IEN0 Register (see also Table 32) EX6 EX5 EX4 EX3 IP0.5 IP0.4 IP0.3 IP0.2 Table 29: The IP0 Register (see also Table 45) © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB ET0 EX0 LSB EX2 LSB IP0.1 IP0.0 V2.5 ...

Page 27

... LCALL. Page 3-Phase Energy Meter Table 31: The WDTREL Register Table 32: The WDTREL Bit Functions © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB 1 0 V2.5 ...

Page 28

... EX6=0 – disable external interrupt 6 EX5=0 – disable external interrupt 5 EX4=0 – disable external interrupt 4 EX3=0 – disable external interrupt 3 EX2=0 – disable external interrupt 2 Table 36: The IEN1 Bit Functions © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB ET0 EX0 LSB EX2 V2 ...

Page 29

... Table 38: The IEN2 Bit Functions TF0 TR0 IE1 IT1 Table 39: The TCON Register Table 40: The TCON Bit Functions EX6 IEX5 IEX4 Table 41: The IRCON Register © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB - - ES1 LSB IE0 IT0 LSB IEX3 IEX2 V2 ...

Page 30

... Note 1: If clearing of both flags is not performed, then no edge can occur to trigger interrupt 6 later resulting in the ISR for the XFER_BUSY ceasing to run. Page 3-Phase Energy Meter IC Table 42: The IRCON Bit Functions Polarity see DIO_Rx see DIO_Rx Table 43: External MPU Interrupts © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Flag Reset automatic automatic falling automatic falling automatic ...

Page 31

... Table 44: Control Bits for External Interrupts Serial channel 1 interrupt - - - - - - Table 45: Priority Level Groups © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Description External interrupt 0 flag External interrupt 1 flag External interrupt 2 flag External interrupt 3 flag External interrupt 4 flag External interrupt 5 flag ...

Page 32

... Serial channel 1 interrupt Timer 0 interrupt External interrupt 2 External interrupt 1 External interrupt 3 Timer 1 interrupt External interrupt 4 Serial channel 0 interrupt External interrupt 5 External interrupt 6 Table 49: Interrupt Polling Sequence © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 LSB IP0.1 IP0.0 LSB IP1.1 IP1.0 V2.5 ...

Page 33

... Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 Table 50: Interrupt Vectors © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Interrupt Vector Address 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 0x004B ...

Page 34

... Selection > IRCON IRCON.2 IRCON.3 > IRCON.4 IRCON.5 Figure 7: Interrupt Structure © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET rru pt Priority Enable ent IEN0.7 IEN0.0 IP1.0/ IP0.0 IEN2.0 IEN0.1 IP1.1/ IEN1.1 IP0 ...

Page 35

... Multi-use DIO2=P2 (SFR 0xA0 DIO_DIR2 (SFR 0xA1 © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Multi-use DIO1=P1 (SFR 0x90 ...

Page 36

... Resource Selected for DIO Pin Value 0 NONE 1 Reserved 2 T0 (counter0 clock (counter1 clock) 4 High priority I/O interrupt (INT0 rising) 5 Low priority I/O interrupt (INT1 rising) 6 High priority I/O interrupt (INT0 falling) 7 Low priority I/O interrupt (INT1 falling) © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 1 output V2.5 ...

Page 37

... Program and non-volatile Non-volatile data Battery-buffered MPU data RAM Volatile CE data Configuration RAM Volatile (I/O RAM) Volatile CE Program code Table 54: MPU Data Memory Map © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Wait States Memory Size (at 5MHz) (bytes 64KB 2KB ...

Page 38

... COMPSTAT register. VBIAS is used as the threshold, and built-in hysteresis prevents each comparator from repeatedly responding to low-amplitude noise. Page 3-Phase Energy Meter IC 71M651X XIN crystal XOUT Figure 9: Oscillator Circuit © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 39

... Applications section for details). Page 3-Phase Energy Meter IC SEG1 SEG2 SEG3 … P12 ... P5 P9 P13 … P6 P10 P14 ... P7 P11 P15 ... © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 SEG27 … SEG41 P108 ... P164 P109 ... P165 P110 ... P166 P111 ... P167 V2.5 ...

Page 40

... MPU firmware must clear WD_OVF. The WD_OVF bit is also cleared by the RESETZ pin. Page 3-Phase Energy Meter IC VOLTAGE BOOST VDRV LCD_IBST LCD_BSTEN GNDD GNDD V2P5NV V3P3D VOLT REG V3P3D VBAT 0.1V GNDD GNDD V2P5 V2P5 VLCD Figure 10: LCD Voltage Boost Circuitry © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 41

... Page 3-Phase Energy Meter IC V1 V3P3 WDT dis- V3P3-10mV abled V3P3 - 400mV Normal operation, WDT enabled when (V1 < VBIAS) VBIAS the battery is enabled Battery or reset mode 0V Figure 11: Voltage Range for V1 © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 42

... R 1 RX_ACK TX_ACK 3 CMD[3:0] Page 71M6513/71M6513H 3-Phase Energy Meter interface. Polarity Description Positive 1 when an illegal command is received. Positive 1 when serial data bus is busy. Negative 0 indicates that the EEPROM sent an ACK bit. Negative 0 indicates when an ACK bit has been sent to the EEPROM ...

Page 43

... V2_OK (Comparator 2 Output) digital V3_OK (Comparator 3 Output) digital RXD (from Optical interface) digital MUX_SYNC digital CK_10M digital CK_MPU -- reserved for production test digital RTCLK digital CE_BUSY digital XFER_BUSY Table 57: TMUX[3:0] Selections © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 44

... Page 3-Phase Energy Meter IC LCD Segment SSI Signal Output Pin SCLK SEG3 SSDATA SEG4 SFR SEG5 SRDY SEG6 Table 58: SSI Pin Assignment SRDY high-active). If SRDY does not delay it, the first SFR © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 45

... The described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. Page 3-Phase Energy Meter IC Theory of Operation t ∫ Current [A] Voltage [V] Energy per Interval [Ws] Accumulated Energy [Ws © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 15 20 time [ms] V2.5 ...

Page 46

... ADC MUX Frame Conversions (MUX_DIV=6 is shown) MUX_DIV ADC1 ADC2 ADC3 600 900 1200 INITIATED OPCODE AT END OF SUM INTERVAL © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Settle ADC4 ADC5 1500 1800 MAX CK COUNT 140 BEGIN SSI TRANSFER ...

Page 47

... FLAG FLAG Figure 14: RTM Output Format If 16bit fields SSI_BEG Next field is delayed while SRDY is low © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 FLAG If 32bit fields If SSI_CKGATE = ...

Page 48

... Post- Processor Processor I/O RAM (Configuration RAM) Figure 17: MPU/CE Data Flow CE/MPU Communication ⋅ 2520 = = = ACC 32768 Hz f 2520 . © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Processed Metering Data , the product of SUM_CYCLES and ACC = 999 . 75 ms V2.5 ...

Page 49

... APULSEW APULSER EXT_PULSE DATA SAMPLES CE_BUSY CE XFER_BUSY INTERRUPTS Figure 18: MPU/CE Communication (Functional) FLASH CE_EN XFER Interrupt Fault, Reset, Power-Up © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET DISPLAY (me- mory-mapped LCD segments) SERIAL (UART0/1) MPU EEPROM (I2C) DIO CE PRAM COMPUTATION ENGINE CE DRAM AUGUST 2008 V2 ...

Page 50

... SUPPLY CURRENT 1ms Battery Operation Power Save Modes Software Control CE_EN = 0 ADC_DIS = 1 CKOUTDIS = 1 ECK_DIS = 1 *) FLASH66Z =1 LCD_BSTEN = 0 RTM_EN = 0 MPU_DIV = X Table 59: Power Saving Measures © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 3.3V 1.5V 0V nominal 0mA Typical Savings 0.16mA 1.8mA 0.6mA 0.1mA 0.04mA ...

Page 51

... For the 71M6513, the temperature coefficients TC1 and TC2 are given as constants that represent typical component behavior. For the 71M6513H, the temperature characteristics of the chip are measured during production and then stored in the fuse registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in the Electrical Specifications section ...

Page 52

... Figure 21: Chop Polarity w/ Automatic Chopping Accumulation Interval m+1 MUX alt. MUX cycle n cycle Re- Re- Positive Positive versed versed © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Accumulation Interval m+2 MUX MUX cycle n cycle 1 Re- Re- Positive Positive versed versed Accumulation Interval m+2 alt ...

Page 53

... VMAX IMAX 66 . 1782 = Kh ⋅ ⋅ ⋅ WRATE N X ACC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET Accumulation Interval m+2 alt. MUX MUX MUX cycle n cycle 2 cycle 3 cycle re- re- Positive Positive versed 01 11 (11) (11) (11 pulse ] AUGUST 2008 ...

Page 54

... Additionally, by setting the I/O RAM register ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with the emulator. See the cautionary note in the I/O RAM Register description! Page 3-Phase Energy Meter IC Program Security © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 55

... OPT_TXDIS DIO_EEX DIO_PW DIO_R1[2:0] DIO_R3[2:0] DIO_R5[2:0] DIO_R7[2:0] DIO_R9[2:0] DIO_R11[2:0] Real Time Clock: LCD Display Interface: LCD_EN LCD_MODE[2:0] … © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Bit 2 Bit 1 Bit 0 TMUX[3:0] WD_OVF EX_RTC EX_XFR COMP_STAT[2:0] MPU_DIV MUX_ALT FLASH66Z MUX_E DIO_PV ...

Page 56

... TRIM[7:0] Bit 5 Bit 4 Bit 3 Digital I/O: Interrupts and WD Timer: INT5 INT4 INT3 Flash: FLSH_ERASE[7:0] FLSH_PGADR[6:0] Serial EEPROM: EEDATA[7:0] EECTRL[7:0] © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 SSI_FPOL SSI_RDYEN SSI_RDYPOL Bit 2 Bit 1 Bit 0 (Port 0) DIO_0[7:0] DIO_DIR0[7:0] (Port 1) DIO_1[7:0] DIO_DIR1[7:0] (Port 2) ...

Page 57

... Programs the direction of DIO pins 7 through 0. 1 indicates output. Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW for special option for DIO6 and DIO7 outputs. See DIO_EEX for special option for DIO4 and DIO5. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Multiple NONE ...

Page 58

... FLSH_PGADR @ SFR 0xB7. 0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled. Any other pattern written to FLSH_ERASE will have no effect. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 59

... VLC 2 VLCD R/W The LCD bias mode. 000: 4 states, 1/3 bias 001: 3 states, 1/3 bias 010: 2 states, ½ bias 011: 3 states, ½ bias 100: static display © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 11 LCD ...

Page 60

... R/W MUX_SYNC enable. When high, converts SEG7 into a MUX_SYNC output. R/W Tristates the OPT_TX output. R Indicates that the preboot sequence is active. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 DIO DIO4-21 DIO4-20 DIO4-19 DIO4-18 DIO4-17 ...

Page 61

... R/W SFR pulse polarity: 0: positive, 1: negative R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is configured as SRDY. Otherwise LCD driver. R/W SRDY polarity: 0: positive, 1: negative © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 62

... It is powered by the VBAT pin and at boot-up will indicate if the part is recovering from a WD overflow or a power fault. This bit should be cleared by the MPU on boot-up also automatically cleared when RESETZ is low. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

Page 63

... ADC conversion and the number of conversions per cycle must be 12 (allowing for one Page 3-Phase Energy Meter IC CE Program and Environment - where SAG_THR is the LSB value in the description of SAG_THR. LSB LSB © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 . S V2.5 ...

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... The information given in the following tables apply to CE code Version CE13B09D. Page 3-Phase Energy Meter IC Element Input Mapping W0SUM/ W1SUM/ VAR0SUM VAR1SUM VA*IA - VA*(IA-IB)/2 VA*IA VB*IB VA*(IA-IB)/2 - VA*(IA-IB)/2 VB*(IC-IB)/2 VA*IA VB*IB CE RAM Locations © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 W2SUM/ I0SQ I1SQ VAR2SUM SUM SUM - (IA-IB VC*IC IA-IB IB ...

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... IA Phase A current 0x01 VA Phase A voltage 0x02 IB Phase B current 0x03 VB Phase B voltage 0x04 IC Phase C current 0x05 VC Phase C voltage 0x06 TEMP Temperature V3 monitor/comparator 0x07 V3 input Description See description of CE status word below © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

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... For example sag threshold of 80V RMS is desired SAG _ THR − ⋅ ⋅ VMAX . 7 8798 10 Number of consecutive voltage samples below SAG_THR before a sag alarm is declared (80*397µs = 31.8ms). -13 VMAX IMAX / In_8 Wh. -13 VMAX IMAX / In_8 VARh. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 9 V2.5 ...

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... IMAX In_8 - VMAX VMAX ⋅ F VxSQSUM = S Vx RMS N © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 − ⋅ 6 587 - 9.4045* IMAX ⋅ ⋅ ⋅ LSB 3600 F S ACC V2.5 ...

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... PH_AtoC_X *360/N ACC The number of zero crossings the pre- vious accumulation inter- val. Edge crossings are either direction and are debounced. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 FREQU_SEL = 2 Phase lag from VC to VA. +2.4 ACC PH_AtoB_X*360/N ACC Phase lag from VC to VB. ...

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... Filtered, unscaled reading from temperature sensor. This value should be written to TEMP_NOM during meter calibration. Scales all voltage and current inputs. 16384 provides unity gain. Default is 16384. If EXT_TMP = 0, GAIN_ADJ is updated by the CE. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET -22 *(TEMP_RAW_X-TEMP_NOM). ⎛ ⋅ ...

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... The actual pulse rate, using WSUM as an example, is: ⋅ ⋅ X WRATE WSUM = RATE 46 2 Where F = 2520.6Hz (sampling frequency), and X = pulse speed factor derived from CE variables PULSE_SLOW and S PULSE_FAST (see table below). Page 3-Phase Energy Meter IC ⋅ © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

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... DIO_PV bit). The output pulse rate is: -32 0 APULSER * WRATE * 2 S This input is buffered and can be updated by the MPU during a computation interval. The change will take effect at the beginning of the next interval. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 PULSE_SLOW PULSE_FAST - ...

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... Scale factor for the VAR calculation. The default value of KVAR should never 6448 need to be changed. Offset for low-current measurement on V3. 0 -13 LSB = = 9.4045*10 IMAX © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET 14 = 16384. The gain of each channel is directly 15 – desired to delay the current by the ⋅ Φ 02229 ...

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... Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 Figure 26: 71M6513H Wh Accuracy over Current at Various Temperatures Page 3-Phase Energy Meter IC Wh Accuracy at Room Temperature Figure 24: Wh Accuracy, 0.3A - 200A/240V VARh Accuracy at Room Temperature 0 Linearity over Temperature ...

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... Test performed at current distortion amplitude of 40% and voltage distortion amplitude of 10% as per IEC 62053, part 22. Figure 27: Meter Accuracy over Harmonics at 240V, 30A Meter Accuracy over Temperature (71M6513H -10 -15 -60 Figure 28: Typical Meter Accuracy over Temperature Relative to 25°C (w/ Temperature Compensation) ...

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... The first process applied to the 71M6513H is the trimming of the reference voltage, which is guaranteed to have accuracy over temperature of better that ±10PPM/°C. The second process applied to the 71M6513H is the characterization of the reference voltage over temperature. The coefficients for the reference voltage are stored in so-called trim fuses (I/O RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0] ...

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... Energy Meter IC Measured Nominal Frequency [Hz] +50 32767.98 +25 32768.28 0 32768.38 -25 32768.08 -50 32767.58 Table 61: Frequency over Temperature -50 -25 0 Figure 31: Crystal Frequency over Temperature © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 Deviation from Nominal Frequency [PPM] -0.61 8.545 11.597 2.441 -12.817 25 50 V2.5 ...

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... MAIN_EDGE_X address. This count is equivalent to twice the line frequency, and can be used to synchronize and/or correct the RTC production electricity meter, the 71M6513 or 71M6513H is not the only component contributing to temperature de- pendency. In fact, a whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will exhibit slight or pronounced temperature effects ...

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... Figure 33: Connecting LCDs V3P3 V3P3 71M6513 71M6513 VDRV VDRV VLCD VLCD LCD_FS LCD_FS LCD_EN LCD_EN Figure 34: LCD Boost Circuit © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 segments segments commons commons 5VDC 5VDC 5V LCD 5V LCD segments segments commons commons ...

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... Connecting I2C EEPROMs 3kΩ 3kΩ 71M6513 71M6513 3kΩ 3kΩ EEPROM EEPROM DIO4 DIO4 DIO5 DIO5 Figure 35: EEPROM Connection Connecting 5V Devices V3P3 71M651X RX Figure 36: Interfacing 0-5V Signal © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V3P3 V3P3 SCL SCL SDA SDA V2.5 ...

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... Connecting V1 and Reset Pins 10kΩ 10kΩ Figure 38: Voltage Divider for V1 should be around 10Ω. The capacitor C 2 © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 1 1 V3P3SYS V3P3SYS V1 V1 should be 1nF. R1 and C1 should 1 V2.5 ...

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... A reference guide for firmware development on the 71M6513 and 71M6513H is available as a separate document (Software User’s Guide, “SUG”). The User’s Manuals supplied with the Demo Kits contain MPU address maps for the demo code as well as other useful information, such as sample calibration procedures ...

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... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GNDA. Page 3-Phase Energy Meter IC Electrical Specifications © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 −0. 0.5V -0. ...

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... CONDITION Normal Operation Battery Backup No Battery Battery Backup CONDITION V3P3D I = 1mA LOAD V3P3D 15mA LOAD I = 1mA LOAD I = 15mA LOAD VIN=0V VIN=V3P3D © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 MIN TYP MAX UNIT 3.0 3.3 3 3.45 V 2.9 5.5 V Externally Connect to V3P3D 2.0 3.8 V -40 85 º ...

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... CKMPU=38.4kHz Normal Operation as above, except write Flash at maximum rate. ≤25°C Battery backup, V3P3A=V3P3D=VLCD= 32kHz 85°C OSC CONDITION Reduce V3P3 until V2P5 drops 200mV RESETZ=1, iload=0 © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 MIN TYP MAX UNIT 6.4 9.5 mA 3.7 4.3 mA 2.5 4.8 mA ...

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... Ta = -40ºC to +85º 25º 25º -40ºC to 85º 1mA, -1mA LOAD CONDITION Crystal connected © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET MIN TYP MAX UNIT 1.193 1.195 1.197 40 2.5 2 TC2 µV/°C µV/°C − ...

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... SOURCE I =20mA SINK |Vin|≤300mV CONDITION T =25ºC, T =75º Nominal relationship: N(T -40ºC to +85ºC A © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 MIN TYP MAX UNIT mV -250 250 peak -10 10 μV/V - kΩ ...

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... LCD_BSTEN=1 CONDITION With respect to VLCD With respect to VLCD*0.7 With respect to 2*VLCD/3 With respect to VLCD/2 With respect to VLCD/3 With respect to VLCD/2 ΔI =10µA LOAD CONDITION CONDITION © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 MIN TYP MAX UNIT OSC/2 Hz 1.2 2.75 mA 1.2 2 ...

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... CONDITION CKMPU = 4.9MHz CKMPU = 1.25MHz -40°C to +85°C 20,000 25°C 85°C CONDITION CONDITION CKMPU=4.9MHz, Using interrupts CKMPU=4.9MHz, “bit- banging” DIO4/5 © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 MIN TYP MAX UNIT - - - ...

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... Bypass capacitor for V1 Bypass capacitor for VBIAS Boost charging capacitor Boost bypass capacitor Bypass capacitor for V2P5 Resistor for TEST © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 VALUE UNIT ≥0.1±20% μF ≥0.1±20% μ ...

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... LQFP PACKAGE OUTLINE (Bottom View) 14.000 +/- 0.200 0.225 +/- 0.045 Notes: Controlling dimensions are in mm. Page 3-Phase Energy Meter IC Packaging Information 16.000 +/- 0.300 100 MAX. 1.600 1.50 +/- 0.10 0.50 TYP. Side View © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 1 0.10 +/- 0.10 0.60 TYP> V2.5 ...

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... Pinout (Top View) GNDD 1 E_RXTX 2 OPT_TX 3 TMUXOUT 71M6513-IGT/71M6513H-IGT SEG3/SCLK 6 VDRV 7 CKTEST 8 V3P3D 9 SEG4/SSDATA 10 SEG5/SFR 11 E_TBUS[3] 12 E_TBUS[2] 13 E_TBUS[1] 14 E_TBUS[0] 15 SEG37/DIO17 16 SEG38/DIO18 17 DIO_0 18 DIO_1 19 DIO_2 20 DIO_3 21 COM0 22 COM1 23 COM2 24 COM3 25 Page 3-Phase Energy Meter IC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET ...

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... Voltage Reference for the ADC. A 0.1µF capacitor to GNDA should be connected to this pin. Crystal Inputs: A 32kHz style crystal should be connected across these pins. Typically, a 20pF capacitor is also connected from each pin to GNDA. See crystal manufacturer datasheet for details. Voltage boost output. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

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... Emulator handshake. This pin has an internal pull-up resistor. 4 Emulator clock. This pin has an internal pull-up resistor Emulator reset. This pin has an internal pull-up resistor. For TERIDIAN internal use. Must be connected to GNDD via a 10kΩ 7 resistor. © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V2.5 ...

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... GNDA Comparator Input Equivalent Circuit Type 7: Comparator Input V3P3D Oscillator To Pin Oscillator GNDD Oscillator Equivalent Circuit Type 8: Oscillator I/O © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 V3P3A from VREF internal Pin reference GNDA VREF Equivalent Circuit Type 9: VREF V3P3D ...

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... DIO_0-DIO_3, DIO/SEG, RX, OPT_RX pins. Added explanation of SRDY polarity. Page 3-Phase Energy Meter IC ORDERING INFORMATION ORDERING NUMBER 71M6513-IGT/F 71M6513-IGTR/F 71M6513H-IGT/F 71M6513H-IGTR/F . Added notes and clarifications on flash write MUX_DIV © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 PACKAGE MARKING 71M6513-IGT 71M6513-IGT 71M6513H-IGT 71M6513H-IGT V2.5 ...

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... TSC assumes no liability for applications assistance. TERIDIAN Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com Page 3-Phase Energy Meter IC © 2005-2008 TERIDIAN Semiconductor Corporation 71M6513/71M6513H DATA SHEET AUGUST 2008 rd UART in 8/12/2008 ...

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