spear-09-h022 STMicroelectronics, spear-09-h022 Datasheet

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spear-09-h022

Manufacturer Part Number
spear-09-h022
Description
Spear Head Arm 926, 200k Customizable Easic Gates, Large Ip Portfolio Soc
Manufacturer
STMicroelectronics
Datasheet

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Part Number:
spear-09-h022EP
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ARM 926, 200K customizable eASIC™ gates, large IP portfolio SoC
Features
Order codes
September 2006
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
ARM926EJ-S - f
32 KI - 16 KD cache, 8 KI - KD TCM, ETM9 and
JTAG interfaces
200K customizable equivalent ASIC gates
(16K LUT equivalent) with 8 channels internal
DMA high speed accelerator function and 112
dedicated general purpose I/Os
Multilayer AMBA 2.0 compliant Bus with
f
Programmable internal clock generator with
enhanced PLL function, specially optimized for
E.M.I. reduction
16 KB single port SRAM embedded
Dynamic RAM interface:
16 bit DDR, 32 / 16 bit SDRAM
SPI interface connecting serial ROM and Flash
devices
2 USB 2.0 Host independent ports with
integrated PHYs
USB 2.0 Device with integrated PHY
Ethernet MAC 10/100 with MII management
interface
3 independent UARTs up to 115 Kbps
(Software Flow Control mode)
I
6 General Purpose I/Os
MAX
2
C Master mode - Fast and Slow speed
SPEAR-09-H022
Part number
133 MHz
MAX
266 MHz,
Op. Temp. range, °C
-40 to 85
Rev 5
PBGA420 (23x23x1.81 mm)
Overview
SPEAr Head200 is a powerful digital engine
belonging
customizable System on Chips.
The device integrates an ARM core with a large
set of proven IPs (Intellectual Properties) and a
configurable logic block that allows very fast
customization
solutions, with low effort and low investment.
Optimized for embedded applications.
ADC 8 bits, 230 Ksps, 16 analog input
channels
Real Time Clock
WatchDog
4 General Purpose Timers
Operating temperature: - 40 to 85 °C
Package: PBGA 384+36 6R (23x23x1.81 mm)
Package
to
SPEAR-09-H022
of
SPEAr
PBGA420
SPEAr™ Head200
unique
family, the innovative
and/or
PRELIMINARY DATA
Packing
Tray
proprietary
www.st.com
1/71
1

Related parts for spear-09-h022

spear-09-h022 Summary of contents

Page 1

... IPs (Intellectual Properties) and a configurable logic block that allows very fast customization solutions, with low effort and low investment. Optimized for embedded applications. Package - PBGA420 (23x23x1.81 mm) Rev 5 SPEAR-09-H022 SPEAr™ Head200 PRELIMINARY DATA PBGA420 to SPEAr family, the innovative of unique ...

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... Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.11 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.12 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.13 Customizable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Functional pin groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Special I/ 5.2.1 2/71 Memory on chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multi-port memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 USB 2.0 host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 USB 2.0 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet 10/100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB 2.0 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPEAR-09-H022 ...

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... SPEAR-09-H022 5.2.2 6 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 SPEAr Head200 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1.1 7.1.2 8 ARM926EJ Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2 Reset and PLL change parameters sequence . . . . . . . . . . . . . . . . . . . . . 35 9.3 Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 Vectored interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.2 Vector interrupt controller flow sequence . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.3 Simple interrupt flow sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 ...

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... Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 19 General purpose I/ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 20.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 21 Real time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4/71 Transfer rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Hardware mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Software mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Booting from external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 USB2.0PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 UHC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 USB2.0PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 UDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 USB plug detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 SPEAR-09-H022 ...

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... SPEAR-09-H022 22 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 23 General purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 24 Customizable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 24.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 24.2 Custom project development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 24.2.1 24.2.2 24.3 Customization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 24.4 Power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 24.4.1 24.4.2 24.4.3 25 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 25.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 25.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 25.2.1 25.2.2 26 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SPEAr Head behavioral model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 External FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Bitstream download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Connection startup ...

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... Pull-up and Pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 21. LVCMOS DC input specification (3 < VDD < 3.6 Table 22. LVCMOS DC output specification (3 < VDD < 3. Table 23. DC input specification of bidirectional SSTL pins (2.3 < VDD DDR < 2. Table 24. DC input specification of bidirectional differential SSTL pins . . . . . . . . . . . . . . . . . . . . . . . 68 Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6/71 SPEAR-09-H022 ...

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... SPEAR-09-H022 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 2. ARM926EJ-S block diagram Figure 3. Clock system block interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 4. State machine of clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 5. Oscillator board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6. Model for crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 7. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 8. DMA State Machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 9. Data packet transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 10 ...

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... Reference documentation 1 Reference documentation 1. ARM926EJ-S - Technical Reference Manual 2. AMBA 2.0 Specification 3. EIA/JESD8-9 Specification 4. USB2.0 Specification 5. OCHI Specification 6. ECHI Specification 7. UTMI Specification 8. USB Specification 9. IEEE 802.3 Specification 2 10 Bus Specification 8/71 SPEAR-09-H022 ...

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... SPEAR-09-H022 2 Product Overview SPEAr Head200 is a powerful System on Chip based on 110nm HCMOS and consists of 2 main parts: an ARM based architecture and an embedded customizable logic block. The high performance ARM architecture frees the user from the task of developing a complete RISC system. ...

Page 10

... I/Os are available. To allow a simple development of project, customizable logic can be emulated by an external FPGA, where customer can map his logic; FPGA is easy linkable and keeps the access to all on-chip and I/Os interfaces of the macro. 10/71 SPEAR-09-H022 ...

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... SPEAR-09-H022 3 Features 3.1 CPU ARM926EJ-S RISC Processor ● ARM926EJ-S RISC Processor ● f 266 MHz (downward scalable) MAX ● Virtual address support with MMU ● instruction CACHE (4 way set associative) ● data CACHE (4 way set associative) ● instruction TCM ● ...

Page 12

... UDC 2.0 controller with embedded PHY ● High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint ● USB Self-Power mode ● DMA FIFO ● Master interface for DMA transfer to DRAM memory ● AHB slaves for: configuration, Plug autodetect ● Endpoints on the top of endpoint 0: 3 bulkin / bulkout, 2 isochronous 12/71 SPEAR-09-H022 ...

Page 13

... SPEAR-09-H022 3.6.3 Ethernet 10/100 ● MAC110 controller compliant with IEEE 802.3 standard ● Supporting MII 10/100 Mbits/s ● MII management protocol interface ● TX FIFO (512x36 Dual Port) ● RX FIFO (512x36 Dual Port) ● Master interface for DMA transfer to DRAM memory ● ...

Page 14

... KBytes single-port SRAM or mixing logic and RAM ● 2 dedicated buses, each of them connected with a 4 channel DMA ● 8 interrupt lines (level type) available ● 112 dedicated GP I/Os ● Single VIA mask configurable interconnections ● Emulation by an external FPGA, keeping on-chip and I/O interfaces 14/71 SPEAR-09-H022 ...

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... SPEAR-09-H022 4 Block diagram Figure 1. Block diagram VIC VIC USB 2.0 USB 2 Host Host PHY PHY USB 2.0 USB 2 Host Host PHY PHY C C USB 2.0 USB 2 Device ...

Page 16

... For the functional mode they have D22 to be set to 0 D21 H5 Input Enable / disable PLL bypass E1 I/O eASIC general purpose IO F2 SPEAR-09-H022 -Section 26, here follows the pin list, sorted Function Pin Type Analog buffer, 3.3 V capable TTL input buffer, 3.3 V capable, with Pull Down TTL Schmitt trigger input buffer, 3 ...

Page 17

... SPEAR-09-H022 Table 1. Pin description by functional groups (continued) Group Signal Name eASICGP_IO[2] eASICGP_IO[3] eASICGP_IO[4] eASICGP_IO[5] eASICGP_IO[6] eASICGP_IO[7] eASICGP_IO[8] eASICGP_IO[9] eASICGP_IO[10] eASICGP_IO[11] eASICGP_IO[12] eASICGP_IO[13] eASICGP_IO[14] eASICGP_IO[15] eASICGP_IO[16] eASICGP_IO[17] eASIC eASICGP_IO[18] eASICGP_IO[19] eASICGP_IO[20] eASICGP_IO[21] eASICGP_IO[22] eASICGP_IO[23] eASICGP_IO[24] eASICGP_IO[25] eASICGP_IO[26] eASICGP_IO[27] eASICGP_IO[28] eASICGP_IO[29] eASICGP_IO[30] ...

Page 18

... Ball Direction Function A10 C9 I/O eASIC general purpose IO D9 B10 A11 E9 C10 B11 D10 A12 C11 B12 A13 E10 D11 C12 B13 SPEAR-09-H022 Pin Type TTL bidirectional buffer, 3.3 V capable drive capability ...

Page 19

... SPEAR-09-H022 Table 1. Pin description by functional groups (continued) Group Signal Name eASICGP_IO[66] eASICGP_IO[67] eASICGP_IO[68] eASICGP_IO[69] eASICGP_IO[70] eASICGP_IO[71] eASICGP_IO[72] eASICGP_IO[73] eASICGP_IO[74] eASICGP_IO[75] eASICGP_IO[76] eASICGP_IO[77] eASICGP_IO[78] eASICGP_IO[79] eASICGP_IO[80] eASICGP_IO[81] eASIC eASICGP_IO[82] eASICGP_IO[83] eASICGP_IO[84] eASICGP_IO[85] eASICGP_IO[86] eASICGP_IO[87] eASICGP_IO[88] eASICGP_IO[89] eASICGP_IO[90] eASICGP_IO[91] eASICGP_IO[92] eASICGP_IO[93] eASICGP_IO[94] ...

Page 20

... K21 K22 Ethernet RX input data L19 L20 Input L21 Input Data valid on RX L22 Input Data error detected SPEAR-09-H022 Pin Type TTL bidirectional buffer, 3.3 V capable drive capability TTL bidirectional buffer, 3.3 V capable drive capability TTL input buffer, 3.3 V capable with Pull Down ...

Page 21

... SPEAR-09-H022 Table 1. Pin description by functional groups (continued) Group Signal Name MDC Ethernet MDIO GP_IO[0] GP_IO[1] GP_IO[2] GPI/Os GP_IO[3] GP_IO[4] GP_IO[5] SDA I²C SCL TDO TDI JTAG TMS RTCK TCK nTRST MCLK_in MASTER CLOCK MCLK_out MASTER MRESET RESET MPMCDATA[0] MPMCDATA[1] MPMCDATA[2] ...

Page 22

... SDRAM data Y16 W22 W21 W20 W19 W18 W17 W16 AB8 AA8 Y8 W8 AB9 Output DDR / SDRAM data AA9 Y9 W9 AB10 SPEAR-09-H022 Pin Type LVTTL / SSTL ClassII bidirectional buffer TTL bidirectional buffer, 3.3 V capable drive capability LVTTL / SSTL ClassII bidirectional buffer ...

Page 23

... SPEAR-09-H022 Table 1. Pin description by functional groups (continued) Group Signal Name MPMCADDROUT[9] MPMCADDROUT[10] MPMCADDROUT[11] MPMCADDROUT[12] MPMCADDROUT[13] MPMCADDROUT[14] nMPMCDYCSOUT[0] nMPMCDYCSOUT[1] nMPMCDYCSOUT[2] nMPMCDYCSOUT[3] MPMCCKEOUT[0] MPMCCKEOUT[1] MPMCCLKOUT[0] nMPMCCLKOUT[0] MPMCCLKOUT[1] MPMC nMPMCCLKOUT[1] MPMCDQMOUT[0] MPMCDQMOUT[1] MPMCDQMOUT[2] MPMCDQMOUT[3] MPMCDQS[0] MPMCDQS[1] nMPMCCASOUT nMPMCRASOUT nMPMCWEOUT SSTL_VREF RTCXO RTC RTCXI ...

Page 24

... Uart1 TX data N21 Input Uart2 RX data N22 Output Uart2 TX data P19 Input Uart3 RX data P20 Output Uart3 TX data SPEAR-09-H022 Pin Type TTL bidirectional buffer, 3.3 V capable drive capability TTL bidirectional buffer, 3.3 V capable drive capability TTL bidirectional buffer, 3.3 V capable drive capability, ...

Page 25

... SPEAR-09-H022 Table 1. Pin description by functional groups (continued) Group Signal Name DMNS DPLS HOST1_DP HOST1_DM HOST2_DP HOST2_DM HOST1_VBUS HOST2_VBUS USBs OVERCURH1 OVERCURH2 VBUS RREF Table 2. Pins belonging to POWER group Group Signal Name vdde3v3 vdd gnde vdd2v5 thermal_gnd POWER anavdd_3v3_adc anagnd_3v3_adc VREFP_adc ...

Page 26

... Dedicated USB 3.3 V power J3 Dedicated USB 3.3 V power W5 Dedicated USB ground W2 Dedicated USB ground U5 Dedicated USB ground R3 Dedicated USB ground N4 Dedicated USB ground N2 Dedicated USB ground M2 Dedicated USB ground J2 Dedicated USB ground L2 Dedicated USB ground J5 Dedicated USB ground K2 Dedicated USB ground SPEAR-09-H022 Function ...

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... SPEAR-09-H022 5.2 Special I/Os 5.2.1 USB 2.0 Transceiver SPEAr Head has three USB 2.0 UTMI + Multimode ATX transceivers. One transceiver will be used by the USB Device controller, and two will be used by the Hosts. These are all integrated into a single USB three-PHYs macro. 5.2.2 DRAM Data and address buses of Multi-Port Memory Controller used to connect to the banks memory are constituted of programmable pins ...

Page 28

... GPIO 0 → GPIO 5 0x1200_6FFF 0x1200_7FFF I²C 0x1200_8FFF UART 1 0x1200_9FFF UART 2 0x1200_AFFF UART 3 0x1200_BFFF ADC 0x1200_CFFF gDMA 1 0x1200_DFFF gDMA 2 0x120F_FFFF Default Slave 0x12FF_FFFF Default Slave eASIC™ 0x1300_03FF Programmable Interface 0x13FF_FFFF Default Slave SPEAR-09-H022 NOTES 64 MB (on reset before the remap) 256 MB ...

Page 29

... SPEAR-09-H022 Table 3. Memory map (continued) START ADRESS 0x1400_0000 0x1600_0000 0x1A00_0000 0x2000_0000 Write transactions on the APB Bus are all considered 32 bit wide unless otherwise stated. All the access to the Default Slave will cause an abort exception. Memory map is repeated starting from the address 0x8000_0000. ...

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... MB of logic memory space associated to DRAM in the range 0x0000_0000 - 0x0FFF_FFFF. Table 5. Memory Mapping after reset after remapping ADDRESS RANGE 0x9600_0000 - 0x99FF_FFFF 0x0000_0000 - 0x0FFF_FFFF 30/71 SIZE [MB] DESCRIPTION 64 64 Serial Flash (remap) SIZE [MB] DESCRIPTION 64 256 SPEAR-09-H022 Serial Flash Serial Flash DRAM ...

Page 31

... SPEAR-09-H022 7.1.2 Booting sequence A simple initial description of the boot process is showed in the following steps: 1. Power on to fetch the RESET vector at 0x0000_0000 (from the aliased-copy of Serial Flash). 2. Perform any critical CPU initialization at this time. 3. Load into the Program Counter (PC) the address of a routine that will be executed ...

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... KB of instruction CACHE ● data CACHE ● instruction TCM (Tightly Coupled Memory) ● data TCM ● AMBA Bus interface ● Coprocessor interface ● JTAG ● ETM9 (Embedded Trace Macro-cell) for debug; large size version. Figure 2. ARM926EJ-S block diagram 32/71 SPEAR-09-H022 ...

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... SPEAR-09-H022 9 Clock and reset system 9.1 Overview The Clock System block is a fully programmable block able to generate all clocks necessary at the chip, except for USB 2.0 Host and Device controllers, which have a dedicated PLL. The clocks, at default operative frequency, are: ● clock @ 266 MHz for ARM system ● ...

Page 34

... CLOCK CLOCK SYSTEM SYSTEM SYSTEM MRESET MRESET MRESET DIRECTION SIZE [bit] Input Input Output Input SPEAR-09-H022 MCLK_out MCLK_out MCLK_out internal clocks internal clocks internal clocks Table 6 Clock System I/O off-chip DESCRIPTION 1 Oscillator input (12 MHz) 1 External clock in Test mode Oscillator output. It supplies the ...

Page 35

... SPEAR-09-H022 9.2 Reset and PLL change parameters sequence Figure 4 shows a simplified flow chart of clock system FSM. The system remains in an IDLE state until RESET signal is asserted: RESET When RESET = 0 the FSM change state and reaches the PLL PWR-UP state; when PLL locks (PLL_LOCK = 1), means that the PLL_OUT signal oscillates at 264 MHz and the PLL starts to work, so that the FSM advances in the next states ...

Page 36

... Parameters for 12 MHz crystal # L1 (uH) Model 1 6200 Model 2 7500 Model 3 Model 4 17465 36/ Crystal 10 pF Table 7 Parameters for 12 MHz Crystal specifies the (fF) R1 (Ohm) 15.7 10 13.2 15 470 94.6 14.5 10.08 12.45 SPEAR-09-H022 MCLK_in 1 MOhm MCLK_out Figure pF) Notes: 7 3.3 11.6 2.75 11.9965MHz Taitien Model for ...

Page 37

... SPEAR-09-H022 10 Vectored interrupt controller 10.1 Overview The Vector Interrupt Controller provides a software interface to interrupt system, in order to determine the source that is requesting a service and where the service routing is loaded. It supplies the starting address, or vector address, of the service routine corresponding to the highest priority requesting interrupt source. ...

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... Branch to the correct ISR 6. Execute the ISR 7. Clear the interrupt. If the request was generated by a software interrupt, the VICSoftIntClear register must be written too 8. Check the VICIRQStatus register to ensure that no other interrupt is active. If there is an active request go to Step 4 9. Return from Interrupt 38/71 SPEAR-09-H022 ...

Page 39

... SPEAR-09-H022 10.4 Interrupt sources in SPEAr Head200 Table 8. Interrupt sources in SPEAr Head200 INTERRUPT LINE Vectored interrupt controller SOURCE eASIC0 eASIC1 eASIC2 eASIC3 SMI RTC USB HOST 1 – OHCI USB HOST 2 – ...

Page 40

... As a DMA requests are received, the Request Logic will arbiter between them and set the channel request signal. When a channel request is asserted, the State Machine starts a data transfer: first a data packet is transferred from a source to the DMA channel and then from the FIFO to the destination. 40/71 SPEAR-09-H022 ...

Page 41

... SPEAR-09-H022 11.2 DMA control state machine Figure 8. DMA State Machine diagram The DMA control SM is always reset into the IDLE state channel request is asserted, SM moves to READ state and the AHB Master will start a data packet transfer; SM selects appropriate source address. ...

Page 42

... BANK NUMBER SIZE [bit] PRIORITY 32 Max Bus Matrix - Reserved 32 eASIC™ 32 USB 2.0 Device SPEAR-09-H022 ROW LENGTH COLUMN LENGTH MASTER ...

Page 43

... SPEAR-09-H022 Table 10. Multi-Port Memory Controller AHB port assignment (continued) PORT The table is compiled in decreasing order of priority. The I/O interfaces accessible from off-chip are listed here: Table 11. Multi-Port Memory Controller off-chip interfaces SIGNAL MPMCDQS MPMCDATA MPMCCLKOUT nMPMCCLKOUT MPMCCKEOUT MPMCDQMOUT nMPMCRASOUT ...

Page 44

... Only the least 7 bits of these registers are significant because the Delay Lines programming parameter can vary from 0 to 127. Figure 10. MPMC DLL AHB Bus clock HCLK DLL 44/71 10, there are 4 DLLsp. HCLK_DLY DRAM COMMAND DRIVER MPMC SDR DDR SPEAR-09-H022 ADDR, CAS, RAS, WE, .. DDR DATA_OUT CLOCKOUT DLL DATA_IN DQS DQSINL DQSINU DLL ...

Page 45

... SPEAR-09-H022 12.3 SSTLL PAD CONFIGURATION The Stub Series-Terminated Logic (SSTL) interface standard is intended for high-speed memory interface applications and specifies switching characteristics such that operating frequencies up to 200 MHz are attainable. The primary application for SSTL devices is to interface with SDRAMs. ...

Page 46

... The I/O interfaces accessible from off-chip are listed here: Figure 11. SPI Interfaces SMIDATAIN Table 13. SPI signal interfaces description Signal SMIDATAIN SMIDATAOUT SMICLK SMINCS 46/71 SPI Direction Size [bit] Input 1 Output 1 Output 1 Output 4 SPEAR-09-H022 SMINCS SMICLK SMIDATAOUT Description Memory output Memory input Memory clock Bankchip selects (active low) ...

Page 47

... SPEAR-09-H022 At power on the boot code is enabled from the static memory Bank0 by default; this has Flash bank memory. Moreover, at power on, the memory clock signal is 19 MHz, the Release Deep Power-Down is 29 µs and the base address for external memories is 0. ...

Page 48

... SMI Supported instructions OPCODE 13.2.2 Memory map External memory is mapped in AHB address space as shown in Figure 13. Memory map 48/71 DESCRIPTION Read data bytes Read data high speed Read status register Write enable Page program Release from deep power-down SPEAR-09-H022 Figure 13. ...

Page 49

... SPEAR-09-H022 where xx is 16, the address of SMI in the memory map is from 0x1600_0000 to 0x19F_FFFF 13.2.3 Operation mode Two operation modes exist: – Hardware mode is used to serve AHB read and write requests. This is the functional mode at reset. – Software mode is used to serve no AHB requests., during normal working In both cases SMI can work: ● ...

Page 50

... MAC110 IP block: it implements the LAN CSMA/CD sublayer for the following families of systems: 10 Mb/s and 100 Mb/s of data rates for baseband and broadband systems Figure 14. Ethernet MAC Controller block diagram AHB Master connected to MPMC AHB Slave 50/71 DMA_MAC Local FIFO DATA RX DMA TX DMA Configuration Conguration register array SPEAR-09-H022 MII I/F MAC110 MIM PHY ...

Page 51

... SPEAR-09-H022 15 USB 2.0 Host 15.1 Overview SPEAr Head has two fully independent USB 2.0 Hosts and each one is constituted with 2 main blocks: ● the USB2.0PHY that executes the serialization and the de-serialization and implements the transceiver for the USB line. ● the USB2.0 Host Controller (UHC connected on AHB Bus and generates the commands for USB2 ...

Page 52

... DMA Provided with a master interface on the AHB Bus, it manage data transfer between Device Controller CRSs and the FIFO embedded in the block. 16.1.4 USB plug detect The Plug Detect detects when the Device is connected to an Host and is receiving the VBUS signal. 52/71 SPEAR-09-H022 ...

Page 53

... SPEAR-09-H022 17 UART UART provides a standard serial data communication with transmit and receive channels that can operate concurrently to handle a full-duplex operation. Two internal FIFO for transmitted and received data, deep 16 and wide 8 bits, are present; these FIFO can be enabled or disabled through a register. ...

Page 54

... The interface is connected to the I²C bus by a data pin (SDA) and by a clock pin (SCL). SDA signal is synchronized by SCL signal. 54/ bus-specific sequencing, protocol, arbitration APB Register Interface Array 2 C mode (400 KHz bus-specific sequencing, protocol, arbitration and timing SPEAR-09-H022 2 C bus mode. SLC Control I²C BUS SDA Control ...

Page 55

... SPEAR-09-H022 18.2 Operating mode Communication flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated by software. The first byte following the start condition is the address byte always transmitted in Master mode ...

Page 56

... When the acknowledge bit is received, the interface sets Event Flag and the Byte Transfer Finish bits with an interrupt. To close the communication: after writing the last byte to the DR register, set the Stop bit to generate the Stop condition. 56/71 Figure 17 Transfer sequencing EV5). Then the slave Figure 17 Transfer sequencing EV7). Figure 17 Transfer sequencing EV8). SPEAR-09-H022 ...

Page 57

... SPEAR-09-H022 Error Cases ● BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the Event Flag and BERR bits are set by hardware with an interrupt. ● AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt. To resume, set the Start or Stop bit. In all these cases, the SCL line is not held low ...

Page 58

... The GPIO block consists of 6 General Purpose IOs which act as buffers between the IO pads and the processor core: data is stored in the GPIO block and can be written to and read from by the processor via the APB Bus. Figure 18. GPIO block diagram 58/71 SPEAR-09-H022 ...

Page 59

... SPEAR-09-H022 20 ADC 20.1 Overview The ADC integrated in SPEAr Head200 is the ST-ADC8MUX16 and it is connected to APB Bus successive approximation ADC and its main features are: ● 8 bit resolutions ● 230 Ksps ● 16 analog input channels (0 - 3.3 V) ● INL ± 1 LSB ● ...

Page 60

... Time and calendar value are stored in binary code decimal format. The RTC provides also a self-isolation mode, which allows it working even if power isn't supplied to the rest of the device APB Bus slave. 60/71 SPEAR-09-H022 ...

Page 61

... SPEAR-09-H022 22 Watchdog timer The WdT is based on a programmable 8 bit counter and generates a hot reset (single pulse) when it overflows. This reset will restart the ARM but the code will not be downloaded again. The timer should be cleared by the software before it overflows. The counter is clocked by a slow signal coming from a 17 bit prescaler clocked by the APB clock ...

Page 62

... Single Shot Mode. When the timer is enabled, the counter is cleared and starts incrementing. When it reaches the compare register value, an interrupt source is activated, the counter stopped and the timer disabled. The current timer counter value could be read from a register. 62/71 SPEAR-09-H022 ...

Page 63

... SPEAR-09-H022 24 Customizable logic 24.1 Overview The Customizable Logic consists of an embedded macro where it is possible embedding a custom project by mapping up to 200K equivalent ASIC gates (corresponding at 16K LUT). The logic is interfaced with the rest of the system so that can be implemented: ● AHB sub-systems with masters and slaves (via 1 AHB full master, 1 AHB full slave, 1 AHB master lite, 2 AHB slave ports) ● ...

Page 64

... Both Bitstream and VIA-mask realize the user-defined customization for the entire device. The eASIC™ mapping flow starts from the RTL description of the user-defined customization, with the purpose to generate the VIA-mask and configuration Bitstream. 64/71 SPEAR-09-H022 SPEAr™ Head AHB BUS AHB BUS ...

Page 65

... SPEAR-09-H022 24.4 Power on sequence Once the system is powered-on, the eASIC™ logic has to be properly configured before its usage. In order to accomplish this task, two main operations have to be performed (both using dedicated software routines running on the ARM9 microprocessor): 1. Bitstream download 2. Startup of connection between the eASIC™ MacroCell and the rest of the device Both steeps are driven by the a control register programmable via APB bus ...

Page 66

... Input and Output pins; user determined PORT neglected, an approximate relationship between P PORT And, solving first equations: 66/71 Parameter PORT (Tj + 273 ° 273 °C) + Θ · SPEAR-09-H022 Value 2.1 6.4 6.4 6.4 5.4 2.1 6.4 6.4 5.4 6.4 6.4 6.4 -40 to 125 -55 to 150 · Θ is ...

Page 67

... SPEAR-09-H022 constant for the particular, which can be determined through last equation by measuring P at equilibrium, for a know T D Using this value of K, the value of P equation, iteratively for any value of T 25.2 DC electrical characteristics 25.2.1 Supply voltage specifications The recommended operating conditions are listed in the following table: Table 17 ...

Page 68

... Test Condition Vout ≥ Voh (min) or Vout ≤ Vol (max) Vin = 0 or Vin =VDD Parameter Test Condition VDD = min, Iol = 100 µA VDD = min, Ioh = -100 µA Parameter Min. -0.3 SSTL_VREF + 0.15 Parameter SPEAR-09-H022 Min. Typ. Max 110 30 60 133 ...

Page 69

... SPEAR-09-H022 26 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 70

... Changed Block diagram & Pin out. 4 Modified Table 2: Pins belonging to POWER Modified Chapter 2: Product Modified Chapter 3.6.2: USB 2.0 5 Modified Table 2: Pins belonging to POWER Modified Section 16.1.2: Modified Table 16: Absolute maximum rating SPEAR-09-H022 Changes group. Overview: point 9. device. group: ball “AB2”. UDC. values. ...

Page 71

... SPEAR-09-H022 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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