wm8973lgefl-v Wolfson Microelectronics plc, wm8973lgefl-v Datasheet
wm8973lgefl-v
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... Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96kHz generated internally from master clock 5x5x0.9mm QFN package APPLICATIONS MP3 Player / Recorder AAC/WMA/Multi-Format Player / Recorder Minidisc Player / Recorder Portable Digital Music Systems at http://www.wolfsonmicro.com/enews/ WM8973L / 3.3V load Production Data, September 2005, Rev 4.2 Copyright 2005 Wolfson Microelectronics plc ...
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WM8973L DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 BLOCK DIAGRAM .................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATION CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7 OUTPUT PGA’S LINEARITY ......................................................................................... 9 HEADPHONE OUTPUT THD VERSUS ...
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Production Data IMPORTANT NOTICE ..........................................................................................61 ADDRESS.................................................................................................................... 61 w WM8973L PD Rev 4.2 September 2005 3 ...
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... WM8973L PIN CONFIGURATION ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE WM8973LGEFL/V - +85 C WM8973LGEFL/RV - +85 C Note: Reel quantity = 3500 w PACKAGE MOISTURE SENSITIVITY LEVEL 32-lead QFN (5x5x0.9mm) MSL3 (Pb-free) 32-lead QFN (5x5x0.9mm) MSL3 (Pb-free, tape and reel) Production Data PEAK SOLDERING TEMPERATURE ...
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Production Data PIN DESCRIPTION PIN NO NAME Digital Input 1 MCLK Supply 2 DCVDD Supply 3 DBVDD 4 DGND Supply 5 BCLK Digital Input / Output 6 DACDAT Digital Input 7 DACLRC Digital Input / Output 8 ADCDAT Digital Output ...
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WM8973L ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics ...
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Production Data ELECTRICAL CHARACTERISTICS Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T data unless otherwise stated. PARAMETER Analogue Inputs (LINPUT1, RINPUT1, LINPUT2, RINPUT2, LINPUT3, RINPUT3) to ADC out Full Scale Input Signal Level (for ...
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WM8973L Test Conditions DCVDD = 1.5V, DBVDD = 3.3V, AVDD = HPVDD = 3.3V, T data unless otherwise stated. PARAMETER Speaker Output (LOUT2/ROUT2 with 8 Output Power at 1% THD Abs. Max Power Ouptut Total Harmonic Distortion Signal to Noise ...
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Production Data OUTPUT PGA’S LINEARITY 10.000 0.000 Output PGA Gains -10.000 -20.000 -30.000 -40.000 -50.000 -60.000 -70.000 40 50 2.000 1.750 Output PGA Gain Step Size 1.500 1.250 1.000 0.750 0.500 0.250 0.000 ...
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WM8973L HEADPHONE OUTPUT THD VERSUS POWER 0 Headphone Pow er vs THD+N (32Ohm load) -20 -40 -60 -80 -100 Headphone Pow er vs THD+N (16Ohm load) -20 -40 -60 -80 -100 ...
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Production Data SPEAKER THD AND NOISE VERSUS POWER w WM8973L PD Rev 4.2 September 2005 11 ...
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WM8973L POWER CONSUMPTION The power consumption of the WM8973L depends on the following factors. Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings, especially in the digital sections of the WM8973L. Operating ...
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Production Data SIGNAL TIMING REQUIREMENTS SYSTEM CLOCK TIMING MCLK Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse ...
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WM8973L Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Bit Clock Timing Information BCLK rise time (10pF load) BCLK fall time (10pF load) BCLK duty cycle (normal mode, BCLK = MCLK/n) BCLK duty ...
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Production Data CONTROL INTERFACE TIMING – 3-WIRE MODE SCLK SDIN Figure 4 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK ...
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WM8973L CONTROL INTERFACE TIMING – 2-WIRE MODE SDIN SCLK Figure 5 Control Interface Timing – 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, T otherwise stated. PARAMETER Program Register Input Information SCLK Frequency ...
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Production Data INTERNAL POWER ON RESET CIRCUIT AVDD Figure 6 Internal Power on Reset Circuit Schematic The WM8973 includes an internal Power-On-Reset Circuit, as shown in Figure 6, which is used to reset the digital logic into a default state ...
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WM8973L DEVICE DESCRIPTION INTRODUCTION The WM8973L is a low power audio codec offering a combination of high quality audio, advanced features, low power and small size. These characteristics make it ideal for portable digital audio applications such as MP3 and ...
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Production Data The signal inputs are biased internally to the reference voltage VREF. Whenever the line inputs are muted or the device placed into standby mode, the inputs are kept biased to VREF using special anti-thump circuitry. This reduces any ...
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WM8973L MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (i.e. before the ADC the digital domain (after the ADC). ...
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Production Data PGA CONTROL The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user or by ...
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WM8973L ANALOGUE TO DIGITAL CONVERTER (ADC) The WM8973L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input ...
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Production Data REGISTER R5 (05h) ADC and DAC Control R27 (1Bh) Table 10 ADC Signal Path Control Table 11 ADC High Pass Filter Enable Modes w BIT LABEL ADDRESS 6:5 ADCPOL [1:0] 4 HPOR 0 ADCHPD 5 HPFLREN HPFLREN ADCHPD ...
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WM8973L DIGITAL ADC VOLUME CONTROL The output of the ADCs can be digitally amplified or attenuated over a range from –97dB to +30dB in 0.5dB steps. The volume of each channel can be controlled separately. The gain for a given ...
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Production Data AUTOMATIC LEVEL CONTROL (ALC) The WM8973L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal ...
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WM8973L REGISTER ADDRESS R17 (11h) ALC Control 1 R18 (12h) ALC Control 2 R19 (13h) ALC Control 3 Table 13 ALC Control PEAK LIMITER To prevent clipping when a large signal occurs just after a period of quiet, the ALC ...
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Production Data NOISE GATE When the signal is very quiet and consists mainly of noise, the ALC function may cause “noise pumping”, i.e. loud hissing noise during silence periods. The WM8973L has a noise gate function that prevents noise pumping ...
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WM8973L 3D STEREO ENHANCEMENT The WM8973L has a digital 3D enhancement option to artificially increase the separation between the left and right channels. This effect can be used for recording or playback, but not for both simultaneously. Selection of 3D ...
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Production Data OUTPUT SIGNAL PATH The WM8973L output signal paths consist of digital filters, DACs, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8973L is in ‘playback only’ or ‘record and playback’ mode. The ...
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WM8973L GRAPHIC EQUALISER The WM8973L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: Linear bass control: ...
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Production Data DIGITAL TO ANALOGUE CONVERTER (DAC) After passing through the graphic equaliser filters, digital ‘de-emphasis’ can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). De-emphasis ...
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WM8973L OUTPUT MIXERS The WM8973L provides the option to mix the DAC output signal with analogue line-in signals from the LINPUT1/2/3, RINPUT1/2/3 pins or a mono differential input (LINPUT1 – RINPUT1) or (LINPUT2 – RINPUT2), selected by DS (see Table ...
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Production Data REGISTER ADDRESS R36 (24h) Right Mixer Control (1) R37 (25h) Right Mixer Control (2) Table 23 Right Output Mixer Control REGISTER ADDRESS R38 (26h) Mono Mixer Control (1) R39 (27h) Mono Mixer Control (2) Table 24 Mono Output ...
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WM8973L ANALOGUE OUTPUTS LOUT1/ROUT1 OUTPUTS The LOUT1 and ROUT1 pins can drive a 16 Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, ...
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Production Data LOUT2/ROUT2 OUTPUTS The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can also drive an 8 speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so ...
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WM8973L ENABLING THE OUTPUTS Each analogue output of the WM8973L can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To ...
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Production Data REGISTER ADDRESS R24 (18h) Additional Control (2) Table 32 Headphone Switch Figure 11 Example Headset Detection Circuit Using Normally-Open Switch Figure 12 Example Headset Detection Circuit Using Normally-Closed Switch w BIT LABEL DEFAULT 6 HPSWEN 0 5 HPSWPOL ...
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WM8973L THERMAL SHUTDOWN The speaker and headphone outputs can drive very large currents. To protect the WM8973L from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 0 150 C and the thermal shutdown circuit is ...
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Production Data LINE OUTPUT The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs. Additionally, OUT3 and MONOOUT can be used as a stereo line-out by setting OUT3SW=11 (reg. 24) and ensuring the contents of registers 38 and ...
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WM8973L AUDIO DATA FORMATS In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK ...
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Production Data In DSP/PCM mode, the left channel MSB is available on either the 1 rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, ...
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WM8973L Figure 24 DSP/PCM Mode Audio Interface (mode B, LRP=0, Slave) w Production Data PD Rev 4.2 September 2005 42 ...
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Production Data AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised in Table 34. MS selects audio interface operation in master or slave mode. In Master mode BCLK, ADCLRC and DACLRC ...
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WM8973L MASTER MODE ADCLRC AND DACLRC ENABLE In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that ...
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Production Data CLOCK OUTPUT By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0], register 27(1Bh) bits [8:7] the ADCLRC pin may be configured as a clock output. If ADCLRM is 01 ...
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WM8973L MCLK MCLK ADC SAMPLE RATE CLKDIV2=0 CLKDIV2=1 ‘Normal’ Clock Mode (‘*’ indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 12.288 MHz 24.576 MHz 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 ...
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Production Data CONTROL INTERFACE SELECTION OF CONTROL MODE The WM8973L is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select ...
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WM8973L The WM8973L has two possible device addresses, which can be selected using the CSB pin. CSB STATE Table 42 2-Wire MPU Interface Address Selection POWER SUPPLIES The WM8973L can use up to four separate power supplies: AVDD / AGND: ...
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Production Data REGISTER ADDRESS R25 (19h) Power Management (1) R26 (1Ah) Power Management (2) * The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when ROUT1=1 or ROUT2=1. Table 43 Power Management w BIT LABEL ...
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WM8973L STOPPING THE MASTER CLOCK In order to minimise power consumed in the digital core of the WM8973L, the master clock may be stopped in Standby and OFF modes. If this cannot be done externally at the clock source, the ...
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Production Data REGISTER MAP ADDRESS REGISTER remarks (Bit 15 – (00h) 0000000 Left Input volume R1 (01h) 0000001 Right Input volume R2 (02h) 0000010 LOUT1 volume R3 (03h) 0000011 ROUT1 volume R4 (04h) 0000100 Reserved R5 (05h) 0000101 ...
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WM8973L DIGITAL FILTER CHARACTERISTICS The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type and 3. The performance of Types 0 and 1 is listed in the table below, the ...
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Production Data DAC FILTER RESPONSES 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 28 DAC Digital Filter Frequency Response – Type 0 Figure 29 DAC Digital Filter Ripple – Type 0 0 -20 -40 -60 ...
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WM8973L 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 34 DAC Digital Filter Frequency Response – Type 3 Figure 35 DAC Digital Filter Ripple – Type 3 ADC FILTER RESPONSES 0 -20 -40 -60 -80 ...
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Production Data 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 40 ADC Digital Filter Frequency Response – Type 2 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 Frequency (Fs) Figure 42 ADC Digital ...
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WM8973L -10 0 5000 10000 Frequency (Fs) Figure 46 De-emphasis Frequency Response (44.1kHz -10 0 5000 10000 Frequency (Fs) Figure 48 De-emphasis Frequency Response (48kHz) HIGHPASS FILTER The WM8973L has ...
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Production Data APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 51 Recommended External Components Diagram w WM8973L PD Rev 4.2 September 2005 57 ...
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WM8973L LINE INPUT CONFIGURATION When LINPUT1/RINPUT1 or LINPUT2/RINPUT2 are used as line inputs, the microphone boost and ALC functions should normally be disabled. In order to avoid clipping, the user must ensure that the input signal does not exceed AVDD. ...
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Production Data POWER MANAGEMENT EXAMPLES OPERATION MODE Stereo Headphone Playback Stereo Line-in Record Stereo Microphone Record Mono Microphone Record Stereo Line-in to Headphone Out Phone Call Speaker Phone Call [ROUT2INV = 1] Record Phone Call [L channel = mic with ...
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WM8973L PACKAGE DIMENSIONS FL: 32 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW A3 C SIDE VIEW SEATING PLANE Exposed lead Half ...
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... Production Data IMPORTANT NOTICE Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability ...