wm8940gefl-v Wolfson Microelectronics plc, wm8940gefl-v Datasheet - Page 56

• Manufacturer Part Number: wm8940gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8940
w
Figure 30 PLL and Clock Select Circuit
Table 47 PLL Frequency Ratio Control
The PLL frequency ratio R = f
The PLL output then passes through a fixed divide by 4, and can also be further divided by
MCLKDIV[3:0] (see figure 34). The divided clock (SYSCLK) can be used to clock the WM8940
DSP.
N controls the ratio of the division, and K the fractional part.
REGISTER
ADDRESS
R36
PLL N value
R37
PLL K value 1
R38
PLL K Value 2
R39
PLL K Value 3
N = int R
K = int (2
7
6
5:4
3:0
5:0
8:0
8:0
24
BIT
(R - N))
PLL_POWERDOWN
FRACEN
PLLPRESCALE
PLLN
PLLK [23:18]
PLLK [17:9]
PLLK [8:0]
2
/f
1
LABEL
(see Figure 30) can be set using the register bits PLLK and PLLN:
0
1
00
1100
0Ch
093h
0E9h
DEFAULT
PLL POWER
0=ON
1=OFF
Fractional Divide within the PLL
0=Disabled (Lower Power)
1=Enabled
00 = MCLK input multiplied by 2
(default)
01 = MCLK input not divided (default)
10 = Divide MCLK by 2 before input to
PLL
11 = Divide MCLK by 4 before input to
PLL
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
DESCRIPTION
PD, Rev 4.2, April 2008
Production Data
56