wm8940gefl-v Wolfson Microelectronics plc, wm8940gefl-v Datasheet - Page 71

• Manufacturer Part Number: wm8940gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

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Production Data
5 (05h)
6 (06h)
7 (07h)
REGISTER
ADDRESS
0
15:7
6
5
4:3
2:1
0
15:9
8
7:5
4:2
1
0
15:7
BIT
DAC_LOOPBA
CK
WL8
DAC_COMP
ADC_COMP
ADC_LOOPBA
CK
CLKSEL
MCLKDIV
BCLKDIV
MS
LABEL
0
00
00
0
1
010
0
0000
0
00h
000
0
0
00000
DEFAULT
Reserved
Reserved
Digital loopback function
0=No DAC loopback
1=Loopback enabled, DAC data input is fed directly
into ADC data output.
8 Bit Word Length for companding
0=Word Length controlled by WL
1=8 bits
DAC companding
00=off
01=reserved
10=µ-law
11=A-law
ADC companding
00=off
01=reserved
10=µ-law
11=A-law
Digital loopback function
0=No ADC loopback
1=Loopback enabled, ADC data output is fed directly
into DAC data input.
Reserved
Controls the source of the clock for all internal
operation:
0=MCLK
1=PLL output
Sets the scaling for either the MCLK or PLL clock
output (under control of CLKSEL)
000=divide by 1
001=divide by 1.5
010=divide by 2
011=divide by 3
100=divide by 4
101=divide by 6
110=divide by 8
111=divide by 12
Configures the BCLK and FRAME output frequency,
for use when the chip is master over BCLK.
000=divide by 1 (BCLK=MCLK)
001=divide by 2 (BCLK=MCLK/2)
010=divide by 4
011=divide by 8
100=divide by 16
101=divide by 32
110=reserved
111=reserved
Reserved
Sets the chip to be master over FRAME and BCLK
0=BCLK and FRAME clock are inputs
1=BCLK and FRAME clock are outputs generated by
the WM8940 (MASTER)
Reserved
DESCRIPTION
PD, Rev 4.2, April 2008
Digital Audio
Interfaces
Digital Audio
Interfaces
Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
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Digital Audio
Interfaces
REFER TO
WM8940
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