isppac-powr1208p1 Lattice Semiconductor Corp., isppac-powr1208p1 Datasheet
isppac-powr1208p1
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isppac-powr1208p1 Summary of contents
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... POR IN3 CREF IN4 Description The Lattice ispPAC-POWR1208P1 incorporates both in- system programmable logic and in-system programma- ble analog circuits to perform special functions for power supply sequencing and monitoring. The ispPAC- POWR1208P1 device has the capability to be config- ured through software to control up to eight outputs for ...
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... The ispPAC-POWR1208P1 device contains an internal PLD that is programmable by the user to imple- ment digital logic functions and control state machines. The internal PLD connects to four programmable timers, special purpose I/O and the programmable monitoring circuit blocks ...
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... Test Data In, 50k Ohm Internal Pull-up (JTAG Pin) Test Mode Select, 50k Ohm Internal pull-up (JTAG Pin) Voltage Monitor Input 1 Voltage Monitor Input 2 Voltage Monitor Input 3 Voltage Monitor Input 4 Voltage Monitor Input 5 Voltage Monitor Input 6 Voltage Monitor Input 7 3-3 ispPAC-POWR1208P1 Data Sheet Description ...
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... CLK is the PLD clock output in master mode re-routed as an input in slave mode. The clock mode is set in software during design time. In output mode open-drain type pin and requires an external pull-up resistor. Multiple ispPAC-POWR1208P1 devices can be tied together with one acting as the master, the master can use the internal clock and the slave can be clocked by the master. The slave needs to be set up using the clock as an input. 4. The CREF pin requires a 0.1µ ...
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... Conditions ° 3. ≤ 1.8V MON ° 3. > 1.8V MON -40°C to +85° 3.3V DD input ° 3-5 ispPAC-POWR1208P1 Data Sheet Min. Max. 2.7 5.5 3.0 5.5 2.25 5.5 0 5.5 0 6.0 1000 — -40 +85 -40 +85 pin with appropriate DDINP Min. Typ. Max. — — Min ...
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... SOURCE FET Driver in OFF state DD. Conditions 1 V ramping ramping ramping 3.3V in <10µ 0.1µF REF VDD ramping down DD. 3-6 ispPAC-POWR1208P1 Data Sheet Min. Typ. Max. 8 — 12 -10 — 10 — 0.5 — 0.5 — 50 — 10 — — 15 — — 8 — ...
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... V TRIP External clock applied (Note 1) (Note 1) Over Recommended Operating Conditions Conditions 0V ≤ V ≤ DDINP 25 °C 25 ° 4mA SINKOUT (Note 1) (Note 1) (Note 1) Parameter 3-7 ispPAC-POWR1208P1 Data Sheet Min. Typ. Max. — 100mV TRIP 100mV TRIP 0.8 1 0.8 — 1.95 — 0.03 — Min. ...
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... DIH DOZH DOV t DO Over Recommended Operating Conditions Conditions Conditions 1 2 CMOS cells. t CKMIN MSS DOXZ 3-8 ispPAC-POWR1208P1 Data Sheet Min. Typ. Max. 150 25 Min Typ. Max 1 200 200 200 200 200 40 40 100 40 100 t t PWP, ...
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... Typical Change in Trip Point vs. Temperature - Temperature (°C) 3-9 ispPAC-POWR1208P1 Data Sheet Lower Trip Point Error (TP’s <= 1.8V) (VCC = 3.3V, 25C) Trip Error (%) Lower Trip Point Error (TP’s > 1.8V) (VCC = 3.3V, 25C) Trip Error (%) 60 80 100 ...
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... Attenuation and reference values are set internally using E internal to the device. Theory Of Operation The ispPAC-POWR1208P1 incorporates programmable voltage monitors along with digital inputs and outputs as well as high voltage FET gate drivers to control MOSFETs for ramping up power supply rails. The 16 macrocell 4 ...
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... The following table lists the typical hysteresis versus voltage monitor trip-point. 250kHz Programmable Clock Reference (32 selections) D Comparator Sampling with Flip-flop Hysteresis 3-11 ispPAC-POWR1208P1 Data Sheet Digital Q Filter ON OFF Digital Filter ON/OFF To PLD Array ...
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... Lattice Semiconductor Table 3-2. Comparator Hysteresis vs. Setpoint The fourth subsystem in the ispPAC-POWR1208P1’s input voltage monitor is a synchronizer latch and optional dig- ital filter. The synchronizer flip-flop samples the comparator’s output state synchronously with the internal system clock. Synchronous sampling effectively eliminates the possibility of race conditions occurring in any state-control- lers implemented in the ispPAC-POWR1208P1’ ...
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... Lattice Semiconductor Figure 3-3. ispPAC-POWR1208P1 Macrocell Block Diagram Block Init Product Term PT4 PT3 PT2 PT1 PT0 Polarity Clock Global Reset Power On Reset Global Polarity Fuse for Init Product Term Product Term Allocation 3-13 ispPAC-POWR1208P1 Data Sheet ORP D/T Q CLK Macrocell flip-flop provides ...
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... Filters (12) 4 IN[1.. PT[0..4] 4 PT[5..9] 4 PT[10..14] AND ARRAY 36 Inputs 81 Product Terms 4 PT[70..74] 4 PT[75..79] BLK Init 16 Timer 1 Timer 2 Timer 3 Timer 4 Clock Generation 3-14 ispPAC-POWR1208P1 Data Sheet 16 Logic Macrocells MC0 MC1 MC2 Output Routing Pool MC14 MC15 16 Routing Pool HVOUT1 HVOUT2 HVOUT3 HVOUT4 OUT5 OUT6 OUT7 OUT8 ...
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... Lattice Semiconductor Clock and Timer Systems Figure 3-5 shows a block diagram of the ispPAC-POWR1208P1’s internal clock and timer systems. The PLD clock can be programmed with eight different frequencies based on the internal oscillator frequency of 1MHz. Figure 3-5. Clock and Timer Block Internal OSC 1MHz ...
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... PLD Prescaler Divider 1. Frequency values based on 1MHz clock Because the ispPAC-POWR1208P1’s PLD array is clocked from a divided-down version of the device’s 1MHz main clock, special considerations must be observed for asserting input data reliably recognized by state machines implemented using the device. Data presented to the IN1 through IN4 digital inputs must be asserted for a minimum of at least one PLD clock period (4µ ...
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... Note that if the clock module is configured as “slave” (i.e. the CLK is an input), the actual time-out of the four timers is determined by the external clock frequency. Timer Period Timer Reset Expired Timer ProgrammableTimer Delay 3-17 ispPAC-POWR1208P1 Data Sheet Timer Period Start Timer Timer Expired ProgrammableTimer Delay ...
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... Lattice Semiconductor Master-Slave and PLD Expansion Modes To support designs requiring more I/O or logic resources than those provided by the ispPAC-POWR1208P1 possible to gang a number of devices together add a CPLD to provide additional logic. Figure 3-7 shows an example of slaving a CPLD and two ispPAC-POWR1208P1’ single master device Figure 3-7. Example of ispPAC-POWR1208P1’ ...
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... Output Configuration Modes The output pins for the ispPAC-POWR1208P1 device are programmable for different functional modes. The four outputs HVOUT1-HVOUT4, can be used as FET gate drivers or be programmed as open-drain digital outputs. Figure 3-8 explains the details of the gate driver mode. ...
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... Lattice Semiconductor Predicting MOSFET Turn-on Time Because the ispPAC-POWR1208P1’s MOSFET output drivers source a precise and well-defined output current, it becomes possible to predict MOSFET gate rise times if one knows the value of the load capacitance presented by the MOSFET being driven. The other method is by relating the total gate charge to the gate-to-source voltage. ...
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... The voltage that the pin is capable of driving to is listed in Table 3-6. For each supply range, the charge-pump range will be set by the software. Table 3-6. HVOUT Gate Driver Voltage Range ispPAC-POWR1208P1 Data Sheet (the software assists this process). This voltage is con ...
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... This does not prevent the ispPAC- POWR1208P1 from functioning correctly, however, when placed in a valid serial chain with other IEEE 1149.1 com- pliant devices. Since the ispPAC-POWR1208P1 is used to powerup other devices, it should be programmed in a separate chain from PLDs, FPGAs or other JTAG devices. ...
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... CFG ADDRESS REGISTER (4 bits) PLD DATA REGISTER (81 bits) PLD ADDRESS REGISTER (75 bits) INSTRUCTION REGISTER (6 bits) BYPASS REGISTER (1 bit) TEST ACCESS PORT OUTPUT (TAP) LOGIC LATCH TCK TMS TDO 3-23 ispPAC-POWR1208P1 Data Sheet ANALOG CONFIGURATION E 2 NON-VOLATILE MEMORY (164 bits) PLD AND / ARCH 2 E NON-VOLATILE ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR1208P1 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured, verified, and monitored ...
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... POWR1208P1. The IEEE 1149.1 standard defines the bit code of this instruction to be all ones (111111). The required SAMPLE/PRELOAD instruction dictates the Boundary-Scan Register be connected between TDI and TDO. The ispPAC-POWR1208P1 has no boundary scan register, so for compatibility it defaults to the BYPASS mode whenever this instruction is received. The bit code for this instruction is defined by Lattice as shown in Table 3-7 ...
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... ADDPLD instruction. This instruction also forces the outputs into the SAF- ESTATE. DISCHARGE – This instruction is used to discharge the internal programming supply voltage after an erase or pro- gramming cycle and prepares ispPAC-POWR1208P1 for a read cycle. This instruction also forces the outputs into the SAFESTATE. Part Number ...
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... PROGRAMDIS – This instruction disables the programming mode of the ispPAC-POWR1208P1. The Test-Logic- Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR1208P1. ADDSTATUS – This instruction is used to both connect the status register to TDO (Figure 3-15) and latch the 12 voltage monitor (comparator outputs) into the status register. Latching of the 12 comparator outputs into the status register occurs during Capture-Data-Register JTAG state ...
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... Application Example The ispPAC-POWR1208P1 device has 12 comparators to monitor various power supply levels. The comparators each have a programmable trip point that is programmed by the user at design time. The output of the comparators are latched and optionally filtered before being fed into the PLD logic array to drive the state machine logic or mon- itor logic. The comparator’ ...
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... Lattice Semiconductor Figure 3-17. Typical Application Example: ispPAC-POWR1208P1 Driving [4] FET Switches [4] Digital OE/EN Lines DC/DC + Primary Supply - + DC/DC Primary Supply - + DC/DC Primary Supply - + DC/DC Primary Supply - 12 Analog Inputs VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 ispPAC-POWR1208P1 VMON7 VMON8 Power Sequence VMON9 V DD VMON10 VMON11 VMON12 CLK RESET IN1 ...
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... PAC-Designer. PAC-Designer is an easy-to-use graphical user interface (Figure 3-18) that allows the user to set up the ispPAC-POWR1208P1 to perform given functions, such as timed sequences for power supply and mon- itor trip points for the voltage monitor inputs. The software tool gives the user control over how the device drives the outputs and the functional confi ...
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... JTAG TAP interface and shifts in the JEDEC data bits that set the configuration of all the analog and digital circuitry that the user has defined during the design process. Power to the device must be set at 3.0V to 5.5V during programming, once the programming steps have been com- pleted, the power supply to the ispPAC-POWR1208P1 can be set from 2.7V to 5.5V. Once programmed, the on- 2 chip non-volatile E CMOS bits hold the entire design confi ...
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... PACPOWR1208P1-EV Evaluation Fixture The ispPAC-POWR1208P1 Design Kit includes an engineering prototype board that can be connected to the paral- lel port using a Lattice ispDOWNLOAD cable. It demonstrates proper layout techniques for the ispPAC- POWR1208P1 and can be used in real time to check circuit operation as part of the design process. LEDs are sup- plied to debug designs without involving test equipment. Input and output connections as well as a “ ...
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... A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT ON THE PACKAGE BODY. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. 0.20 C A-B D 44X 0.20 H A-B SEE DETAIL 'A' C LEAD FINISH 0.10 C DETAIL 'A' BASE METAL 3-33 ispPAC-POWR1208P1 Data Sheet BOTTOM VIEW GAUGE PLANE 0.20 MIN. A1 1.00 REF. SYMBOL MIN. NOM 0. 1.35 1 ...
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... IN1 6 44-pin TQFP IN2 7 IN3 8 IN4 9 RESET 10 VDDINP Change Summary 3-34 ispPAC-POWR1208P1 Data Sheet Operating Temperature Range I = Industrial (-40°C to +85°C) Package T = 44-pin TQFP TN = Lead-Free 44-pin TQFP* Performance Grade 01 = Standard Pins 44 Pins 44 VMON2 33 VMON1 32 TMS ...