74LCX14MTC Fairchild Semiconductor, 74LCX14MTC Datasheet

IC INVERTER HEX SCHMT IN 14TSSOP

74LCX14MTC

Manufacturer Part Number
74LCX14MTC
Description
IC INVERTER HEX SCHMT IN 14TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LCXr
Datasheet

Specifications of 74LCX14MTC

Logic Type
Inverter with Schmitt Trigger
Number Of Inputs
1
Number Of Circuits
6
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Logical Function
Inverter Schmit Trig
Logic Family
LCX
Number Of Elements
6
Input Type
Schmitt Trigger
High Level Output Current
-24mA
Low Level Output Current
24mA
Propagation Delay Time
7.8ns
Operating Supply Voltage (typ)
2.5/3.3V
Package Type
TSSOP W
Operating Temp Range
-40C to 85C
Pin Count
14
Quiescent Current
10uA
Output Type
Schmitt Trigger
Technology
CMOS
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
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74LCX14MTC
Manufacturer:
FAIRCHILD
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Part Number:
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©1995 Fairchild Semiconductor Corporation
74LCX14 Rev. 1.7.0
74LCX14
Low Voltage Hex Inverter with 5V Tolerant
Schmitt Trigger Inputs
Features
Ordering Information
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LCX14M
74LCX14SJ
74LCX14BQX
74LCX14MTC
Order Number
5V tolerant inputs
2.3V–3.6V V
6.5ns t
Power down high impedance inputs and outputs
±24mA output drive (V
Implements patented noise/EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance:
– Human body model
– Machine model
Leadless DQFN package
All packages are lead free per JEDEC: J-STD-020B standard.
PD
max. (V
(1)
CC
specifications provided
CC
Package
Number
200V
MLP14A
MTC14
M14A
M14D
3.3V), 10µA I
CC
2000V
3.0V)
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC
MO-241, 2.5 x 3.0mm
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
CC
max.
General Description
The LCX14 contains six inverter gates each with a
Schmitt trigger input. They are capable of transforming
slowly changing input signals into sharply defined, jitter-
free output signals. In addition, they have a greater noise
margin than conventional inverters.
The LCX14 has hysteresis between the positive-going
and negative-going input thresholds (typically 1.0V)
which is determined internally by transistor ratios and is
essentially insensitive to temperature and supply voltage
variations.
The inputs tolerate voltages up to 7V allowing the inter-
face of 5V, 3V and 2.5V systems.
The 74LCX14 is fabricated with advanced CMOS tech-
nology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Package Description
February 2008
www.fairchildsemi.com

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74LCX14MTC Summary of contents

Page 1

... M14A 74LCX14SJ M14D (1) 74LCX14BQX MLP14A 74LCX14MTC MTC14 Note: 1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev ...

Page 2

... Connection Diagrams Pin Assignments for SOIC, SOP, and TSSOP Pad Assignments for DQFN (Top View) Pin Description Pin Names Description I Inputs n O Outputs n ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 Logic Symbol IEEE/IEC Truth Table Input Output www.fairchildsemi.com ...

Page 3

... Output Voltage, HIGH or LOW State Output Current 3.0V–3. 2.7V–3. 2.3V–2.7V CC Note: 3. Unused inputs must be held HIGH or LOW. They may not float. ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 Parameter (2) GND I (3) Parameter 3 Rating –0.5V to +7.0V –0.5V to +7.0V –0. 0.5V CC –50mA –50mA +50mA ± ...

Page 4

... Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 V (V) Conditions CC 2 ...

Page 5

... Dynamic Switching Characteristics Symbol Parameter V Quiet Output Dynamic Peak V OLP V Quiet Output Dynamic Valley V OLV Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT C Power Dissipation Capacitance PD ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 V (V) Conditions CC 3.3 C 50pF, V 3.3V 2.5 C 30pF, V 2.5V 3.3 C 50pF ...

Page 6

... Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t 3-STATE Output Low Enable and Disable Times for Logic Figure 2. Waveforms (Input Characteristics 1MHz, t ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 (Generic for LCX Family) includes probe and jig capacitance) L ...

Page 7

... Schematic Diagram (Generic for LCX Family) ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 7 www.fairchildsemi.com ...

Page 8

... BQX Leader (Start End) Trailer (Hub End) Tape Dimensions inches (millimeters) Reel Dimensions inches (millimeters) Tape Size A 12mm 13.0 (330.0) 0.059 (1.50) ©1995 Fairchild Semiconductor Corporation 74LCX14 Rev. 1.7.0 Tape Section Number of Cavities 125 (Typ.) Carrier 3000 75 (Typ 0.512 (13.00) 0.795 (20.20) ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 12

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 13

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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