tp5322 Supertex, Inc., tp5322 Datasheet
tp5322
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tp5322 Summary of contents
Page 1
... Distance of 1.6mm from case for 10 seconds. P-Channel Enhancement-Mode Vertical DMOS FETs General Description The Supertex TP5322 is a low threshold enhancement- mode (normally-off) transistor utilizing an advanced vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeffi ...
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... 1.0MHz -25V -700mA 25Ω, GEN PULSE GENERATOR R GEN INPUT TP5322 I † DRM (A) (A) -0.7 -0.9 = -2.0mA = -1.0mA D = -1.0mA 125 -25V DS = -100mA D = -200mA D = -200mA D = -200mA D = -500mA = -500mA D ...
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... TO-236AB (SOT-23) Package Outline (K1) 2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch Symbol A A1 MIN 0.89 0.01 Dimension NOM - - (mm) MAX 1.12 0.10 JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999. Drawings not to scale 0.88 0.30 2.80 2.10 1.20 0.95 - 2.90 - 1.30 1.02 0.50 3.04 2.64 1.40 3 TP5322 0.40 0 0.95 1.90 0.54 0.50 BSC BSC REF 0.60 8 θ ...
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... MAX 1.60 0.56 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale. (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TP5322 B122707 0.36 ...