pex-8512 PLX, pex-8512 Datasheet

pex-8512

Manufacturer Part Number

pex-8512

Description

12 Lane, 5 Port Pci Express Switch, 23 X 23mm Pbga

Manufacturer

PLX

Datasheet

1.PEX-8512.pdf (4 pages)

Current page: 1 of 4
Download datasheet (2Mb)

Features

PEX 8512 General Features

o 12-lane PCI Express switch

o Up to five ports

o 23mm x 23mm, 376-ball PBGA

o Typical Power: 2.0 Watts

PEX 8512 Key Features

o Standards Compliant

o High Performance

o Non-Transparent Bridging

o Flexible Configuration

o PCI Express Power Management

o Spread Spectrum Clock

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

- Integrated SerDes

package

- PCI Express Base Specification, r1.1

- Standard SHPC Specification, r1.1

- Non-blocking internal architecture

- Full line rate on all ports

- Cut-Thru latency: 150ns

- Configurable Non-Transparent port

- Up to Five configurable ports (x1, x2

- Configurable with strapping pins,

- Lane and polarity reversal

- Link power management states: L0,

- Device states: D0 and D3hot

- Vaux, WAKE#, Beacon support

- Dual clock domain

- Two Virtual Channels per port

- Eight Traffic Classes per port

- Fixed and Round-Robin Virtual

- Three Standard Hot-Plug Controllers

- Upstream port as hot-plug client

- Transaction Layer end-to-end CRC

- Poison bit

- Advanced Error Reporting

- Lane Status bits and GPO available

- Per port error diagnostics

(hot-plug)

for Multi-Host or Intelligent I/O

Support

and x4)

EEPROM, I

L0s, L1, L2/L3 Ready, L2 and L3

Channel Port Arbitration

• Bad DLLPs

• Bad TLPs

• CRC errors

JTAG boundary scan

Fatal Error out-of-band signal option

Version 1.2 2007

C, or Host software

Multi-purpose, Feature Rich ExpressLane™ PCI Express Switch

The ExpressLane PEX 8512 device offers PCI Express switching capability

enabling users to add scalable high bandwidth, non-blocking interconnection

to a wide variety of applications including servers, storage systems,

communications platforms, blade servers, and embedded-control

products. The PEX 8512 is well suited for fan-out, aggregation, peer-to-

peer, and intelligent I/O module applications.

Highly Flexible Port Configurations

The PEX 8512 offers 12 lanes which can be distributed into three ports or

five ports. In the case of three ports, the ports are configured for symmetric

(each port having the same lane width). The PEX 8512 features a flexible

central packet memory that allocates a memory buffer for each port as

required by the application or endpoint. This buffer allocation along with the

device's flexible packet flow control minimizes bottlenecks when the

upstream and aggregated downstream bandwidths do not match. Any of the

ports can be designated as the upstream port, which can be changed

dynamically.

End-to-end Packet Integrity

The PEX 8512 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require guaranteed error-free packets. These

features are optional in the PCI Express specification, but PLX provides

them across its entire ExpressLane switch product line.

Non-Transparent “Bridging” in a PCI Express Switch

The PEX 8512 supports full non-transparent bridging (NTB) functionality to

allow implementation of multi-host systems and intelligent I/O modules in

applications such as communications, storage, and blade servers. To

ensure quick product migration, the non-transparency features are

implemented in the same fashion as in standard PCI applications.

Non-transparent bridges allow systems to isolate memory domains by

presenting the processor subsystem as an endpoint, rather than another

memory system. Base address registers are used to translate addresses;

doorbell registers are used to send interrupts between the address domains;

and scratchpad registers are accessible from both address domains to allow

inter-processor communication.

Two Virtual Channels

The ExpressLane PEX 8512 switch supports two Virtual Channels (VCs) and

eight Traffic Classes (TCs). The mapping of Traffic Classes to port-specific

Virtual Channels allows for different mappings for different ports. In

addition, the devices offer user-selectable Virtual Channel arbitration

algorithms to enable users to fine tune the Quality of Service (QoS) required

for a specific application.

Flexible & Versatile PCI Express

PEX 8512

Switch

Related parts for pex-8512

pex-8512 Summary of contents

Page 1

... I/O module applications. Highly Flexible Port Configurations The PEX 8512 offers 12 lanes which can be distributed into three ports or five ports. In the case of three ports, the ports are configured for symmetric (each port having the same lane width). The PEX 8512 features a flexible central packet memory that allocates a memory buffer for each port as required by the application or endpoint ...

Page 2

... PCI Express link that needs to be fanned into a larger number of ports for a variety of I/O functions, each with different bandwidth requirements. In this example, the PEX 8512 would typically have a 4-lane upstream port, and two downstream ports. The downstream ports are configured with x4 link widths. ...

Page 3

... NTB function. Non-Transparent Port Expansion Application Primary Primary Primary Primary Host Host Host Host The PEX 8512 can also be utilized to expand the number of CPU CPU CPU CPU CPU CPU PCI Express devices in a given system. Figure 6 shows how Blade Blade Blade Blade ...

Page 4

... RDK into smaller slots. The PEX 8512RDK hardware module can be installed in a motherboard and be used as a riser card. Lane Status Lane Status The PEX 8512RDK can be used to test and validate customer LEDs LEDs software. Additionally, it can be used as an evaluation vehicle for PEX 8512 features and benefits. ...

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