pex-8648 PLX, pex-8648 Datasheet

pex-8648

Manufacturer Part Number

pex-8648

Description

48-lane, 12-port Pci Express Gen 2 5.0 Gt/s Switch, 27 X 27mm Fcbga

Manufacturer

PLX

Datasheet

1.PEX-8648.pdf (4 pages)

Current page: 1 of 4
Download datasheet (245Kb)

Features

o 48-lane, 12-port PCIe Gen 2 switch

o 27 x 27mm

o Typical Power: 4.0 Watts

o Standards Compliant

o High Performance

o Flexible Configuration

o Dual-Host & Fail-Over Support

o Quality of Service (QoS)

o Reliability, Availability, Serviceability

PEX 8648 General Features

PEX 8648 Key Features

- Integrated 5.0 GT/s SerDes

- PCI Express Base Specification, r2.0

- PCI Power Management Spec, r1.2

- Microsoft Vista Compliant

- Supports Access Control Services

- Dynamic link-width control

- Dynamic SerDes speed control

- Non-blocking switch fabric

- Full line rate on all ports

- Packet Cut-Thru with 140ns max packet

- 2KB Max Payload Size

- Read Pacing (bandwidth throttling)

- Dual Cast

- Ports configurable as x1, x2, x4, x8, x16

- Registers configurable with strapping

- Lane and polarity reversal

- Compatible with PCIe 1.0a PM

- Configurable Non-Transparent port

- Moveable upstream port

- Crosslink port capability

- Eight traffic classes per port

- Weighted round-robin source

- 3 Hot-Plug Ports with native HP Signals

- All ports Hot-Plug capable thru I

- ECRC and Poison bit support

- Data Path parity

- Memory (RAM) Error Correction

- INTA# and FATAL_ERR# signals

- Advanced Error Reporting

- Port Status bits and GPIO available

- Per port error diagnostics

- Performance Monitoring

- JTAG AC/DC boundary scan

(backwards compatible w/ PCIe r1.0a/1.1)

latency (x16 to x16)

pins, EEPROM, I

port arbitration

(Hot-Plug Controller on every port)

• Per port payload & header counters

Version 0.95 2008

, 676-pin FCBGA package

C, or host software

The ExpressLane

capability enabling users to add scalable high bandwidth, non-blocking

interconnection to a wide variety of applications including servers, storage

systems, and communications platforms. The PEX 8648 is well suited for

fan-out, aggregation, and peer-to-peer applications.

High Performance & Low Packet Latency

The PEX 8648 architecture supports packet cut-thru with a maximum

latency of 140ns (x16 to x16). This, combined with large packet memory

and non-blocking internal switch architecture, provides full line rate on all

ports for performance-hungry applications such as servers and switch

fabrics. The low latency enables applications to achieve high throughput and

performance. In addition to low latency, the device supports a packet payload

size of up to 2048 bytes, enabling the user to achieve even higher throughput.

Data Integrity

The PEX 8648 provides end-to-end CRC (ECRC) protection and Poison bit

support to enable designs that require end-to-end data integrity. PLX also

supports data path parity and memory (RAM) error correction as packets

pass through the switch.

Flexible Register & Port Configuration

The PEX 8648’s 12 ports can be configured to lane widths of x1, x2, x4, x8,

or x16. Flexible buffer allocation, along with the device's flexible packet

flow control, maximizes throughput for applications where more traffic

flows in the downstream, rather than upstream, direction. Any port can be

designated as the upstream port, which can be changed dynamically. The

PEX 8648 also provides

several ways to

configure its registers.

The device can be

configured through

strapping pins, I

interface, host

software, or an optional

serial EEPROM. This

allows for easy debug

during the development

phase, performance

monitoring during the

operation phase, and

driver or software

upgrade. Figure 1

shows some of the

PEX 8648’s common

port configurations.

PCIe Gen 2, 5.0GT/s 48-lane, 12-port PCIe Switch

PEX 8648

PEX 8648 device offers PCI Express switching

Figure 1. Common Port Configurations

PEX 8648

11 x4

10 x4

2 x8

4 x8

PEX 8648

6x4

2 x4

Related parts for pex-8648

pex-8648 Summary of contents

Page 1

... Flexible Register & Port Configuration The PEX 8648’s 12 ports can be configured to lane widths of x1, x2, x4, x8, or x16. Flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction ...

Page 2

... Gen 1 endpoints. In Figure 3, the PCIe slots connected to the PEX 8648’s downstream ports can be populated with either PCIe Gen 1 or PCIe Gen 2 devices. Conversely, the PEX 8648 can also be used to create Gen 2 ports on a Gen 1 native Chip Set in the same fashion. 2 ...

Page 3

... Point Point Figure 4. Router Usage Backplane Communication With 48 lanes and 12 ports, the PEX 8648 is well suited for backplane applications requiring high connectivity (a large number of ports). Figure 5 represents an ATCA or MicroTCA backplane application with two switch fabric blades and multiple AMC blades. In this example, two PEX 8648s provide peer-to-peer data exchange for AMC blades connecting to the switch fabric ...

Page 4

... The PEX 8648RDK is a hardware module containing the PEX 8648 which plugs right into your system. The PEX 8648RDK can be used to test and validate customer software, or used as an evaluation vehicle for PEX 8648 features and benefits. The PEX 8648RDK provides everything that a user needs to get their hardware and software development started ...

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