a3pn060-zvqg100i Actel Corporation, a3pn060-zvqg100i Datasheet
a3pn060-zvqg100i
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a3pn060-zvqg100i Summary of contents
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... QN48 QN68 QN68 ProASIC3 Advance v0.6 I/O Standards: LVTTL, LVCMOS † and Drive Strength † † † 1 A3PN030 A3PN060 A3PN125 125 k 256 512 1,024 768 1,536 3,072 – – – Yes Yes – ...
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... Height (mm A3PN015 A3PN020 A3PN030 – "ProASIC3 nano Ordering Information" on page III QN48 0.4 0. A3PN060 A3PN125 A3PN250 ProASIC3 Handbook to ensure for the location of QN68 VQ100 196 0.4 0.5 0.90 1.20 ...
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... A3PN250 = 250,000 System Gates Note: *For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input. For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the device ...
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... – – Country of Origin Date Code Customer Mark (if applicable) A3PN125 A3PN250 – – VQ100 VQ100 A3PN060 A3PN125 C, I – – – – Std. ✓ ✓ – – A3PN250 – ...
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ProASIC3 nano Device Overview General Description ProASIC3, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASIC nano devices the advantage of being a secure, low-power, single-chip solution that is live ...
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ProASIC3 nano Device Overview Security, built into the FPGA fabric inherent component of ProASIC3 nano devices. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive ...
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Advanced Flash Technology ProASIC3 nano devices offer many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of ...
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... User Nonvolatile FlashROM Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and A3PN020) ISP AES User Nonvolatile Decryption . Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125 Bank 1 Charge Pumps Bank 1 Bank 0 ...
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ISP AES User Nonvolatile Decryption Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with ...
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... Higher density ProASIC3 nano devices using either the two I/O bank or four I/O bank architectures provide the designer with very flexible clock conditioning capabilities. A3PN060, A3PN125, and A3PN250 contain six CCCs. One CCC (center west side) has a PLL. The A3PN030 and smaller devices use different CCCs in their architecture ...
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... Each I/O module contains several input, output, and enable registers. These registers allow the implementation of various single-data-rate applications for all versions of nano devices and double-data-rate applications for the A3PN060, A3PN125, and A3PN250 devices. ProASIC3 nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support cold-sparing and Schmitt trigger ...
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... Table 1 · ProASIC3 nano Devices (November 2008) A3PN020 and A3PN030. The following table note was removed: "Six chip (main) and three quadrant global networks are available for A3PN060 and above." The QN100 package was removed for all devices. The "Device Marking" section Advance v0 ...
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... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...
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ProASIC3 nano DC and Switching Characteristics General Specifications The Z feature grade does not support the enhanced nano features of Schmitt trigger input, cold- sparing, and hot-swap I/O capability. Refer to the ordering information in the Product Brief ...
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ProASIC3 nano DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions Symbol T Ambient temperature A T Junction temperature 1 core supply voltage CC V JTAG DC voltage JTAG 4 V Programming voltage Programming ...
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Table 2-4 • Overshoot and Undershoot Limits Average V V and VMV Duration as a Percentage of Clock Cycle CCI 2 less 3 V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The ...
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ProASIC3 nano DC and Switching Characteristics Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation where VT can be from 0. 0.9 V ...
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Thermal Characteristics Introduction The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ...
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... V LVCMOS (JESD8-11) Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. Values are for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 have a default loading the total dynamic power measured on V AC10 ...
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Power Consumption of Various Internal Resources Table 2-10 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 nano Devices Parameter Definition P Clock contribution of a Global Rib AC1 P Clock contribution of a Global Spine AC2 P Clock ...
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ProASIC3 nano DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power ...
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Combinatorial Cells Contribution—P α C-CELL C-CELL the number of VersaTiles used as combinatorial modules in the design. C-CELL α is the toggle rate of VersaTile outputs—guidelines are provided in ...
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ProASIC3 nano DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock percentage. If the toggle rate of a net is 100%, this ...
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User I/O Characteristics Timing Model I/O Module (Registered 1. Input LVCMOS 2 0.24 ns ICLKQ t = 0.26 ns ISUD Input LVTTL Clock Register Cell I/O ...
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ProASIC3 nano DC and Switching Characteristics t PY PAD DIN V PAD Y GND DIN GND Figure 2-3 • Input Buffer Timing Model and Delays (example CLK I/O Interface = MAX(t (R), ...
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DOUT D Q CLK D From Array I/O Interface D DOUT PAD Figure 2-4 • Output Buffer Model and Delays (example) ProASIC3 nano DC and Switching Characteristics t DP DOUT t = MAX(t (R ...
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ProASIC3 nano DC and Switching Characteristics t EOUT D Q CLK CLK D I/O Interface D 50 EOUT (R) 50% EOUT t ZL PAD V trip D 50 EOUT (R) 50% EOUT t ...
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Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-14 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Drive Slew ...
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ProASIC3 nano DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-16 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS ...
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... Table 2-18 • Summary of I/O Timing Characteristics—Software Default Settings (at 35 pF) STD Speed Grade, Commercial-Case Conditions: T For A3PN060, A3PN125, and A3PN250 I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 8 1 3.3 V LVCMOS Wide Range Any 2.5 V LVCMOS 8 1.8 V LVCMOS 4 1.5 V LVCMOS 2 Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification ...
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ProASIC3 nano DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-20 • Input Capacitance Symbol C Input capacitance IN C Input capacitance on the clock pin INCLK Table 2-21 • I/O Output Buffer Maximum Resistances Standard 3.3 V LVTTL ...
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Table 2-23 • I/O Short Currents I /I OSH 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS * T = 100°C J The length of time an ...
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... Software default selection highlighted in gray. Test Point Datapath Figure 2-6 • AC Loading Table 2-28 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes: 1. Measuring point = V See trip. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 Min., Max., Max., Min ...
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... Std. 0.60 7.45 –1 0.51 6.33 –2 0.45 5.56 Note: For specific junction temperature and voltage supply levels, refer to values. Table 2-30 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: T Software Default Load for A3PN060, A3PN125, A3PN250 Drive Speed Strength Grade t t DOUT Std. 0.60 7.53 –1 0.51 6.41 –2 ...
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ProASIC3 nano DC and Switching Characteristics Table 2-31 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: T Software Default Load for A3PN020, A3PN015, A3PN010 Drive Speed Strength Grade t DOUT 2 mA Std. ...
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V LVCMOS Wide Range Table 2-33 • Minimum and Maximum DC Input and Output Levels for 3.3 V LVCMOS Wide Range 3.3 V LVCMOS Wide Range V IL Drive Strength Min., V Max Any –0.3 0.8 Notes: ...
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... Software default selection highlighted in gray. Test Point Datapath Figure 2-7 • AC Loading Table 2-35 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes: 1. Measuring point = V See trip. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 Min., Max., Max., Min ...
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... Std. 0.60 8.24 –1 0.51 7.01 –2 0.45 6.15 Note: For specific junction temperature and voltage supply levels, refer to values. Table 2-37 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: T Software Default Load for A3PN060, A3PN125, A3PN250 Drive Speed Strength Grade t t DOUT Std. 0.60 8.54 –1 0.51 7.26 –2 0.45 6 ...
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ProASIC3 nano DC and Switching Characteristics Table 2-38 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: T Software Default Load for A3PN020, A3PN015, A3PN010 Drive Speed Strength Grade t DOUT 2 mA Std. 0.60 –1 0.51 –2 ...
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... Figure 2-8 • AC Loading Table 2-41 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) 0 Notes: 1. Measuring point = V See Table 2-16 on page 2-16 trip. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF. ProASIC3 nano DC and Switching Characteristics Max., Max., Min ...
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... Std. 0.60 –1 0.51 –2 0.45 Note: For specific junction temperature and voltage supply levels, refer to values. Table 2-43 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: T Software Default Load for A3PN060, A3PN125, A3PN250 Drive Speed Strength Grade t DOUT 2 mA Std. 0.60 –1 0.51 –2 0. Std ...
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Table 2-44 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: T Software Default Load for A3PN020, A3PN015, A3PN010 Drive Speed Strength Grade t t DOUT Std. 0.60 8.90 –1 0.51 7.57 –2 0.45 6.65 ...
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... Software default selection highlighted in gray. Test Point Datapath Figure 2-9 • AC Loading Table 2-47 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Notes: 1. Measuring point = V See trip. 2. Capacitive Load for A3PN060, A3PN125, and A3PN250 Max., Min Max., V Min ...
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... DOUT Std. 0.60 13.17 –1 0.51 11.20 –2 0.45 9.83 Note: For specific junction temperature and voltage supply levels, refer to values. Table 2-49 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: T Software Default Load for A3PN060, A3PN125, A3PN250 Drive Speed Strength Grade t t DOUT Std. 0.60 8.10 –1 0.51 6.89 –2 ...
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ProASIC3 nano DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Preset Data C Enable B CLK A Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Figure ...
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Table 2-52 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3 nano DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Data CC Enable BB CLK AA CLR DD Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered Figure 2-11 • ...
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Table 2-53 • Parameter Definition and Measuring Nodes Parameter Name t Clock-to-Q of the Output Data Register OCLKQ t Data Setup Time for the Output Data Register OSUD t Data Hold Time for the Output Data Register OHD t Enable ...
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ProASIC3 nano DC and Switching Characteristics Input Register 50% CLK 50% 1 Data Enable 50% t IHE t Preset ISUE Clear Out_1 Figure 2-12 • Input Register Timing Diagram Timing Characteristics Table 2-54 • Input Data Register Propagation Delays Commercial-Case ...
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Output Register 50% 50% CLK t 1 50% Data_out Enable 50% t OHE t Preset OSUE Clear DOUT Figure 2-13 • Output Register Timing Diagram Timing Characteristics Table 2-55 • Output Data Register Propagation Delays Commercial-Case Conditions: T Parameter t ...
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ProASIC3 nano DC and Switching Characteristics Output Enable Register 50% CLK 1 50% D_Enable 50% Enable t t OESUE OEHE Preset Clear EOUT Figure 2-14 • Output Enable Register Timing Diagram Timing Characteristics Table 2-56 • Output Enable Register Propagation ...
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DDR Module Specifications Input DDR Module INBUF A Data B CLK CLKBUF C CLR INBUF Figure 2-15 • Input DDR Timing Model Table 2-57 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out Out_QR DDRICLKQ1 t Clock-to-Out Out_QF DDRICLKQ2 t ...
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ProASIC3 nano DC and Switching Characteristics CLK Data 1 2 CLR t DDRIREMCLR t DDRICLR2Q1 Out_QF t DDRICLR2Q2 Out_QR Figure 2-16 • Input DDR Timing Diagram Timing Characteristics Table 2-58 • Input DDR Propagation Delays Commercial-Case Conditions: T Parameter t ...
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Output DDR Module A Data_F (from core) B CLK CLKBUF C D Data_R (from core) B CLR INBUF C Figure 2-17 • Output DDR Timing Model Table 2-59 • Parameter Definitions Parameter Name Parameter Definition t Clock-to-Out DDROCLKQ t Asynchronous ...
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ProASIC3 nano DC and Switching Characteristics CLK Data_F DDROREMCLR Data_R CLR DDROREMCLR t DDROCLR2Q Out Figure 2-18 • Output DDR Timing Diagram Timing Characteristics Table 2-60 • Output DDR Propagation Delays Commercial-Case Conditions: T ...
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VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3 library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the ® Fusion, IGLOO ...
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ProASIC3 nano DC and Switching Characteristics OUT GND V CC OUT Figure 2-20 • Timing Model and Waveforms NAND2 or Any Combinatorial Logic MAX PD(FF) applicable ...
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Timing Characteristics Table 2-61 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: T Combinatorial Cell Equation INV AND2 · B NAND2 Y = !(A · B) OR2 NOR2 Y = ...
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ProASIC3 nano DC and Switching Characteristics 50% CLK 50% Data EN 50 PRE SUE CLR Out Figure 2-22 • Timing Model and Waveforms Timing Characteristics Table 2-62 • Register Delays Commercial-Case Conditions: T Parameter t Clock-to-Q of ...
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Global Resource Characteristics A3PN250 Clock Tree Topology Clock delays are device-specific. The global tree presented in device used to drive all D-flip-flops in the device. CCC Figure 2-23 • Example of Global Tree Use in an A3PN250 Device ...
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ProASIC3 nano DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and ...
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... Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to values. Table 2-66 • A3PN060 Global Resource Commercial-Case Conditions: T Parameter Description t ...
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ProASIC3 nano DC and Switching Characteristics Table 2-67 • A3PN125 Global Resource Commercial-Case Conditions: T Parameter Description t Input LOW Delay for Global Clock RCKL t Input HIGH Delay for Global Clock RCKH t Minimum Pulse Width HIGH for Global ...
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Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-69 • ProASIC3 nano CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency f Clock Conditioning Circuitry Output Frequency f Delay Increments in Programmable Delay Blocks Number of Programmable Values in Each ...
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ProASIC3 nano DC and Switching Characteristics Output Signal Note: Peak-to-peak jitter measurements are defined by T Figure 2-24 • Peak-to-Peak Jitter Definition period_max period_min = T – T peak-to-peak period_max period_min ...
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Embedded SRAM and FIFO Characteristics SRAM ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB Figure 2-25 • RAM Models ProASIC3 nano DC ...
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ProASIC3 nano DC and Switching Characteristics Timing Waveforms CLK ADD t BKS BLK_B t ENS WEN_B Figure 2-26 • RAM Read for Pass-Through Output CLK ADD t BKS BLK_B t ENS ...
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CYC t CKH CLK ADD 0 t BKS BLK_B t ENS WEN_B Figure 2-28 • RAM Write, Output Retained (WMODE = 0) t CKH CLK ...
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ProASIC3 nano DC and Switching Characteristics CLK RESET_B Figure 2-30 • RAM Reset CYC t t CKH CKL RSTBQ ...
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Timing Characteristics Table 2-70 • RAM4K9 Commercial-Case Conditions: T Parameter t Address Setup time AS t Address Hold time AH t REN_B, WEN_B Setup time ENS t REN_B, WEN_B Hold time ENH t BLK_B Setup time BKS t BLK_B Hold ...
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ProASIC3 nano DC and Switching Characteristics Table 2-71 • RAM512X18 Commercial-Case Conditions: T Parameter t Address setup time AS t Address hold time AH t REN_B, WEN_B setup time ENS t REN_B, WEN_B hold time ENH t Input data (DI) ...
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FIFO RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE Figure 2-31 • FIFO Model ProASIC3 ...
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ProASIC3 nano DC and Switching Characteristics Timing Waveforms RCLK/ WCLK RESET_B EMPTY AEMPTY FULL AFULL WA/RA (Address Counter) Figure 2-32 • FIFO Reset RCLK EMPTY AEMPTY WA/RA NO MATCH (Address Counter) Figure 2-33 • FIFO EMPTY Flag and AEMPTY Flag ...
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WCLK FULL AFULL WA/RA NO MATCH (Address Counter) Figure 2-34 • FIFO FULL Flag and AFULL Flag Assertion WCLK MATCH WA/RA NO MATCH (EMPTY) (Address Counter) 1st Rising Edge After 1st Write RCLK EMPTY AEMPTY Figure 2-35 • FIFO EMPTY ...
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ProASIC3 nano DC and Switching Characteristics Timing Characteristics Table 2-72 • FIFO Worst Commercial-Case Conditions: T Parameter t REN_B, WEN_B Setup Time ENS t REN_B, WEN_B Hold Time ENH t BLK_B Setup Time BKS t BLK_B Hold Time BKH t ...
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Embedded FlashROM Characteristics t SU CLK t HOLD Address A 0 Data Figure 2-37 • Timing Diagram Timing Characteristics Table 2-73 • Embedded FlashROM Access Time Commercial-Case Conditions: T Parameter Description t Address Setup Time SU t Address Hold Time ...
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ProASIC3 nano DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the Characteristics" ...
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Part Number and Revision Date Part Number 51700111-002-1 Revised November 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version Advance v0.1 Table 2-2 · Recommended Operating Conditions ...
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Package Pin Assignments 48-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource ...
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Package Pin Assignments 48-Pin QFN Pin Number A3PN010 Function 1 GEC0/IO37RSB1 2 IO36RSB1 3 GEA0/IO34RSB1 4 IO22RSB1 5 GND 6 VCCIB1 7 IO24RSB1 8 IO33RSB1 9 IO26RSB1 10 IO32RSB1 11 IO27RSB1 12 IO29RSB1 13 IO30RSB1 14 IO31RSB1 15 IO28RSB1 16 ...
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QFN Pin Number A3PN030Z Function 1 IO82RSB1 2 GEC0/IO73RSB1 3 GEA0/IO72RSB1 4 GEB0/IO71RSB1 5 GND 6 VCCIB1 7 IO68RSB1 8 IO67RSB1 9 IO66RSB1 10 IO65RSB1 11 IO64RSB1 12 IO62RSB1 13 IO61RSB1 14 IO60RSB1 15 IO57RSB1 16 IO55RSB1 17 IO53RSB1 ...
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Package Pin Assignments 68-Pin QFN Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at ...
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QFN Pin Number A3PN015 Function 1 IO60RSB2 2 IO54RSB2 3 IO52RSB2 4 IO50RSB2 5 IO49RSB2 6 GEC0/IO48RSB2 7 GEA0/IO47RSB2 8 VCC 9 GND 10 VCCIB2 11 IO46RSB2 12 IO45RSB2 13 IO44RSB2 14 IO43RSB2 15 IO42RSB2 16 IO41RSB2 17 IO40RSB2 ...
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Package Pin Assignments 68-Pin QFN Pin Number A3PN020 Function 1 IO60RSB2 2 IO54RSB2 3 IO52RSB2 4 IO50RSB2 5 IO49RSB2 6 GEC0/IO48RSB2 7 GEA0/IO47RSB2 8 VCC 9 GND 10 VCCIB2 11 IO46RSB2 12 IO45RSB2 13 IO44RSB2 14 IO43RSB2 15 IO42RSB2 16 ...
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QFN Pin Number A3PN030 Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 IO63RSB1 17 IO62RSB1 ...
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Package Pin Assignments 68-Pin QFN Pin Number A3PN030Z Function 1 IO82RSB1 2 IO80RSB1 3 IO78RSB1 4 IO76RSB1 5 GEC0/IO73RSB1 6 GEA0/IO72RSB1 7 GEB0/IO71RSB1 8 VCC 9 GND 10 VCCIB1 11 IO68RSB1 12 IO67RSB1 13 IO66RSB1 14 IO65RSB1 15 IO64RSB1 16 ...
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VQFP 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx ProASIC3 nano Packaging 3 - ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3PN030 Function 1 GND 2 IO82RSB1 3 IO81RSB1 4 IO80RSB1 5 IO79RSB1 6 IO78RSB1 7 IO77RSB1 8 IO76RSB1 9 GND 10 IO75RSB1 11 IO74RSB1 12 GEC0/IO73RSB1 13 GEA0/IO72RSB1 14 GEB0/IO71RSB1 15 IO70RSB1 16 ...
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VQFP Pin Number A3PN030Z Function 1 GND 2 IO82RSB1 3 IO81RSB1 4 IO80RSB1 5 IO79RSB1 6 IO78RSB1 7 IO77RSB1 8 IO76RSB1 9 GND 10 IO75RSB1 11 IO74RSB1 12 GEC0/IO73RSB1 13 GEA0/IO72RSB1 14 GEB0/IO71RSB1 15 IO70RSB1 16 IO69RSB1 17 VCC ...
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... GDC0/IO46RSB0 59 GDC1/IO45RSB0 60 GCC2/IO43RSB0 61 GCB2/IO42RSB0 62 GCA0/IO40RSB0 63 GCA1/IO39RSB0 64 GCC0/IO36RSB0 65 GCC1/IO35RSB0 66 VCCIB0 67 GND 68 VCC 69 IO31RSB0 70 GBC2/IO29RSB0 71 GBB2/IO27RSB0 72 IO26RSB0 100-Pin VQFP Pin Number A3PN060 Function 73 GBA2/IO25RSB0 74 VMV0 75 GNDQ 76 GBA1/IO24RSB0 77 GBA0/IO23RSB0 78 GBB1/IO22RSB0 79 GBB0/IO21RSB0 80 GBC1/IO20RSB0 81 GBC0/IO19RSB0 82 IO18RSB0 83 IO17RSB0 84 IO15RSB0 85 IO13RSB0 86 IO11RSB0 87 VCCIB0 88 ...
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... GDC1/IO45RSB0 60 GCC2/IO43RSB0 61 GCB2/IO42RSB0 62 GCA0/IO40RSB0 63 GCA1/IO39RSB0 64 GCC0/IO36RSB0 65 GCC1/IO35RSB0 66 VCCIB0 67 GND 68 VCC 69 IO31RSB0 70 GBC2/IO29RSB0 71 GBB2/IO27RSB0 72 IO26RSB0 ProASIC3 nano Packaging 100-Pin VQFP Pin Number A3PN060Z 73 GBA2/IO25RSB0 74 VMV0 75 GNDQ 76 GBA1/IO24RSB0 77 GBA0/IO23RSB0 78 GBB1/IO22RSB0 79 GBB0/IO21RSB0 80 GBC1/IO20RSB0 81 GBC0/IO19RSB0 82 IO18RSB0 83 IO17RSB0 84 IO15RSB0 85 IO13RSB0 86 IO11RSB0 87 VCCIB0 ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3PN125 Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 7 IO130RSB1 8 IO129RSB1 9 GND 10 GFB1/IO124RSB1 11 GFB0/IO123RSB1 12 VCOMPLF 13 GFA0/IO122RSB1 14 VCCPLF 15 GFA1/IO121RSB1 16 ...
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VQFP Pin Number A3PN125Z Function 1 GND 2 GAA2/IO67RSB1 3 IO68RSB1 4 GAB2/IO69RSB1 5 IO132RSB1 6 GAC2/IO131RSB1 7 IO130RSB1 8 IO129RSB1 9 GND 10 GFB1/IO124RSB1 11 GFB0/IO123RSB1 12 VCOMPLF 13 GFA0/IO122RSB1 14 VCCPLF 15 GFA1/IO121RSB1 16 GFA2/IO120RSB1 17 VCC ...
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Package Pin Assignments 100-Pin VQFP Pin Number A3PN250 Function 1 GND 2 GAA2/IO67RSB3 3 IO66RSB3 4 GAB2/IO65RSB3 5 IO64RSB3 6 GAC2/IO63RSB3 7 IO62RSB3 8 IO61RSB3 9 GND 10 GFB1/IO60RSB3 11 GFB0/IO59RSB3 12 VCOMPLF 13 GFA0/IO57RSB3 14 VCCPLF 15 GFA1/IO58RSB3 16 ...
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VQFP Pin Number A3PN250Z Function 1 GND 2 GAA2/IO67RSB3 3 IO66RSB3 4 GAB2/IO65RSB3 5 IO64RSB3 6 GAC2/IO63RSB3 7 IO62RSB3 8 IO61RSB3 9 GND 10 GFB1/IO60RSB3 11 GFB0/IO59RSB3 12 VCOMPLF 13 GFA0/IO57RSB3 14 VCCPLF 15 GFA1/IO58RSB3 16 GFA2/IO56RSB3 17 VCC ...
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... Changes in Current Version (Advance v0.5) pin table for A3PN030 is new. QFN", "68-Pin QFN", and "100-Pin VQFP" pin table for A3PN060Z is new. pin table for A3PN125Z is new pin table for A3PN250Z is new. pin table for A3PN030 is new. pin diagram was revised. "48-Pin QFN" ...
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... Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information ...
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... Actel, IGLOO, Actel Fusion, ProASIC, Libero, Pigeon Point and the associated logos are trademarks or registered trademarks of Actel Corporation. All other trademarks and service marks are the property of their respective owners. Actel is the leader in low-power FPGAs and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions ...