ht82m9ae Holtek Semiconductor Inc., ht82m9ae Datasheet
ht82m9ae
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ht82m9ae Summary of contents
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... PA0~PA7, PB4 and PB7 support wake-up function Internal Power-On reset (POR) Watchdog Timer (WDT) 16 I/O ports 20-pin SOP/SSOP (209mil) package 24-pin SSOP (209mil) package 32-pin QFN package The mask version HT82M9AA is fully pin and functionally compatible with the OTP version HT82M9AE device. 1 April 16, 2008 ...
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... Block Diagram Pin Assignment Rev. 1.60 HT82M9AE/HT82M9AA 2 April 16, 2008 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.60 HT82M9AE/HT82M9AA Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register) ...
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... System Start-up Timer Period SST t Crystal Setup OSC Note: Power-on period WDT SST OSC WDT Time-out in normal mode=1/f WDT Time-out in HALT mode=1/f Rev. 1.60 HT82M9AE/HT82M9AA Test Conditions V Conditions DD No load, f =6MHz 5V SYS No load, system HALT, 5V USB suspend** No load, system HALT, 5V input/output mode, 5V set SUSPEND2 [1CH] ...
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... Return from Subroutine S11 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.60 HT82M9AE/HT82M9AA After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. ...
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... TABRDL [ Note: *11~*0: Table location bits @7~@0: TBLP bits Rev. 1.60 HT82M9AE/HT82M9AA ROM data by two table read instructions: TABRDC and TABRDL , transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The three methods are shown as follows: ...
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... The RAM bank 1 mapping is as shown. Address 00~1FH in RAM Bank0 and Bank1 are located in the same Registers Rev. 1.60 HT82M9AE/HT82M9AA Bank 0 RAM Mapping Indirect Addressing Register Locations 00H and 02H are indirect addressing regis- ters that are not physically implemented. Any read/write operation on [00H] ([02H]) will access the data memory pointed to by MP0 (MP1) ...
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... Bank 1 RAM Mapping Rev. 1.60 HT82M9AE/HT82M9AA Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations. The data movement between two data memory locations must pass through the accumulator. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions ...
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... The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82M9AE/ HT82M9AA, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed ...
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... When the HT82M9AE/HT82M9AA receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82M9AE/HT82M9AA are set and a USB interrupt is triggered. Whenever a USB reset signal is detected, the USB in- terrupt is triggered and URST_Flag bit of the USC regis- ter is set. When the interrupt has been served, the bit should be cleared by firmware ...
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... The WDT and WDT prescaler will be cleared and re- counted again (if the WDT clock is from the WDT os- cillator). Rev. 1.60 HT82M9AE/HT82M9AA Watchdog Timer All of the I/O ports remain in their original status. The PDF flag is set and the TO flag is cleared. The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port WDT overflow ...
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... HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. Reset Timing Chart Rev. 1.60 HT82M9AE/HT82M9AA The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable ...
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... USR 0000 0000 u0uu 0u00 SCC 0000 0000 uu00 u000 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.60 HT82M9AE/HT82M9AA RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 0000 0000 0000 0000 uuuu uuuu ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 1.60 HT82M9AE/HT82M9AA nal (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the f (Timer). The pulse width measurement mode can be used to count the high or low level duration of the exter- nal signal (TMR) ...
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... To function as an input, the corresponding latch Rev. 1.60 HT82M9AE/HT82M9AA of the control register must write The input source also depends on the control register. If the control regis- ter bit the input will read the pad state. If the con- trol register bit the contents of the latches will move to the internal bus ...
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... Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode. Rev. 1.60 HT82M9AE/HT82M9AA The relationship between V ) must LVR ...
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... Register Register R/W Name Address Pipe_ctrl R/W 01000001B STALL R/W 01000011B Endpt_EN R/W 01000111B Pipe_ctrl (41H), STALL (43H) and Endpt_EN (47H) Registers Rev. 1.60 HT82M9AE/HT82M9AA STALL SIES MISC Endpt_EN FIFO 0 43H 45H 46H 47H Register Memory Mapping Bit 5 Bit 4 Bit 3 Bit 2 Address value Default value=00000000 Bit7~Bit3 ...
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... End of transient flag, normal status suspend= 1 line & EOT= 0 indicates that EOT R something is wrong in the USB Interface. The programmer must do something to save the device and keep it alive. MNI R/W This bit is for masking the NAK interrupt when MNI the default value= 0 Rev. 1.60 HT82M9AE/HT82M9AA Read/Write MNI R/W EOT R R/W NAK R ...
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... R/W R/W MISC (46H) Registers Table Description MISC Function Table HT82M9AE/HT82M9AA allows a maximum of 8 bytes of data in each packet. The HT82M9AE/HT82M9AA FIFO is written by packet. To write to FIFO, the following should be followed: Select a set of FIFO, set in the write mode (MISC TX bit = 1), and set the REQ bit to 1 ...
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... USB interrupt is triggered. The follow- ing is the timing diagram: The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of USC). Once the USB Host receive the wake-up signal from the HT82M9AE/HT82M9AA, it will send a Resume 20 Bit7~Bit0 Data7~Data0 Data7~Data0 ...
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... The timing is as follows: Configuring the Device as a PS2 Device The HT82M9AE/HT82M9AA can be defined as a USB interface or a PS2 interface by configuring the SPS2 (bit 4 of the USR) and SUSB (bit 5 of the USR). If SPS2=1, and SUSB=0, the HT82M9AE/HT82M9AA is defined as ...
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... PEC5 R/W 6 PEC6 R/W 7 PEC7 R/W Rev. 1.60 HT82M9AE/HT82M9AA Option Functions USB suspend mode status bit. When 1, indicates that the USB SUSPEND system entry is in suspend mode. RMOT_WK USB remote wake-up signal. The default value When RESUME_OUT EVENT, RESUME_O is set RESUME_O The default value ...
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... CLR WDT , instructions 9 TBHP enable/disable (default: disable output mode (CMOS/NMOS/PMOS) by bit (default: CMOS) Rev. 1.60 HT82M9AE/HT82M9AA Option Functions Reserved, must set USB clock control bit. When set indicates a USBCK ON, USBCKEN else USBCK OFF. The default value This bit is used to reduce power consumption in the suspend mode ...
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... RES to high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible Components with * are used for EMC issue. Components with ** are used for resonator only. Components with *** are used for 12MHz application. Rev. 1.60 HT82M9AE/HT82M9AA 24 April 16, 2008 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.60 HT82M9AE/HT82M9AA Description 25 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.60 HT82M9AE/HT82M9AA Description 26 Instruction Flag Cycle Affected 2 ...
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... ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF PDF ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF addr PDF OV Z ...
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... Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF OV ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA Program Counter+1 PDF PDF PDF ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF Program Counter+1 ...
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... Rotate data memory left and place result in the accumulator Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA Stack PDF Stack PDF ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.60 HT82M9AE/HT82M9AA PDF PDF PDF OV ...
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... Package Information 20-pin SOP (300mil) Outline Dimensions Symbol Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mil Min. Nom. 394 290 14 490 Max. 419 300 20 510 104 April 16, 2008 ...
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... SSOP (209mil) Outline Dimensions Symbol Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mil Min. Nom. 291 196 9 271 65 25. Max. 323 220 15 295 April 16, 2008 ...
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... SSOP (209mil) Outline Dimensions Symbol Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mil Min. Nom. 291 196 9 311 Max. 323 220 15 345 April 16, 2008 ...
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... SAW Type QFN Outline Dimensions Symbol Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mm. Min. Nom. 0.7 0 0.2 0. 0.5 1.25 1.25 0.3 43 Max. 0.8 0.05 0.3 3.25 3.25 0.5 April 16, 2008 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20N (209mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mm 330 1 62 1.5 13.0+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13.0+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 44 April 16, 2008 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 12.5+0.3 0.2 Dimensions in mm 24.0+0.3 0.1 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 45 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.60 HT82M9AE/HT82M9AA Dimensions in mm 16.0+0.3 0.1 12 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 7.1 0.1 7.2 0.1 2 0.1 0.3 0.05 13.3 Dimensions 0.3 8 0.1 1.75 0.1 5.5 0.05 1.5+0.1 1.5+0.25 4 0.1 2 0.05 5.25 0.1 5 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.60 HT82M9AE/HT82M9AA 47 April 16, 2008 ...