ht82k94e Holtek Semiconductor Inc., ht82k94e Datasheet
ht82k94e
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ht82k94e Summary of contents
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... Low battery detector with internal bit Operating voltage from 4.0V to 5.5V (For Connect USB/PS2 Mode) Operating voltage from 2.2V to 3.3V (For Pure Cal. Mode) 32-pin QFN, 48-pin SSOP packages The mask version HT82K94A is fully pin and function- ally compatible with the OTP version HT82K94E device. 1 April 29, 2008 ...
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... Block Diagram Rev. 1.90 HT82K94E/HT82K94A 2 April 29, 2008 ...
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... Wake-up PD5~PD7 Pull-high PE0~PE7 I/O Wake-up Rev. 1.90 HT82K94E/HT82K94A Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by ROM code option. The input or output mode is con- trolled by PAC (PA control register). Pull-high resistor options: PA0~PA7 CMOS/NMOS/PMOS options: PA0~PA7 Wake-up options: PA0~PA7 PA7 is pin-shared with TMR1 input, respectively ...
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... I/O Port Source Current for PA1~PA7, I OH1 PB, PC I/O Port Source Current for PA0 OH2 Rev. 1.90 HT82K94E/HT82K94A Description Negative power supply, ground Schmitt trigger reset input. Active low Positive power supply 3.3V regulator output USBD+ or PS2 CLK I/O line USB or PS2 function is controlled by software control register ...
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... Watchdog Time-out Period (WDT OSC) 5V Without WDT prescaler WDT1 Watchdog Time-out Period t WDT2 (System Clock) t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 1.90 HT82K94E/HT82K94A Test Conditions Min. V Conditions DD 25 2-battery option 2.1 3-battery option 2.3 2-battery option 2.3 3-battery option 2 ...
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... Program Counter+2 *11 * #11 # Program Counter S12~S0: Stack register bits @7~@0: PCL bits 6 HT82K94E/HT82K94A * ...
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... Note: *12~*0: Table location bits @7~@0: Table pointer bits Rev. 1.90 HT82K94E/HT82K94A Location 00CH This location is reserved for the Timer/Event Counter 1 interrupt service program timer interrupt results from a Timer/Event Counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00CH ...
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... Data Memory - RAM for Bank 1 The special function registers used in USB interface are located in RAM bank 1. In order to access the Bank1 Rev. 1.90 HT82K94E/HT82K94A register, only the Indirect addressing pointer MP1 can be used and the Bank register BP should be set The mapping of RAM bank shown. ...
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... TO set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 1.90 HT82K94E/HT82K94A Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence ...
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... USB interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to disable other interrupts. When the PC Host access the FIFO of the HT82K94E/ HT82K94A, the corresponding request bit of the USR is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed ...
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... A crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator. No other external components are required. In stead of Rev. 1.90 HT82K94E/HT82K94A a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required. ...
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... TO flags, the program can distinguish between different chip resets . TO PDF 0 0 RES reset during power- RES reset during normal operation 0 0 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: u stands for unchanged 12 HT82K94E/HT82K94A RESET Conditions April 29, 2008 ...
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... PA 1111 1111 1111 1111 PAC 1111 1111 1111 1111 PB 1111 1111 1111 1111 Rev. 1.90 HT82K94E/HT82K94A The functional unit chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear Clear. After master reset, WDT WDT begins counting ...
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... To enable/disable timer 0 counting (0=disabled; 1=enabled) To define the operating mode 01=Event count mode (external clock) 6 TM0 10=Timer mode (internal clock) 7 TM1 11=Pulse width measurement mode 00=Unused Rev. 1.90 HT82K94E/HT82K94A RES Reset WDT RES Reset (Normal Time-Out (HALT) Operation) (HALT)* 1111 1111 1111 1111 ...
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... Timer/Event Counter 0 preload register and reading TMR0 gets the contents of the Timer/Event Counter 0. The TMR0C is a timer/event counter control register, which defines some options. Rev. 1.90 HT82K94E/HT82K94A Function TMR1C (11H) Register Timer/Event Counter 0 Timer/Event Counter 1 There are 3 registers related to Timer/Event Counter 1; ...
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... The overflow of the Timer/Event Counter 0/1 is one of the wake-up sources. No matter what the oper- ation mode is, writing ET0I/ET1I can disable the corresponding interrupt services. Rev. 1.90 HT82K94E/HT82K94A In the case of Timer/Event Counter 0/1 OFF condition, /4 writing data to the Timer/Event Counter 0/1 preload regis- SYS ter will also reload that data to the Timer/Event Counter 0/1 ...
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... Since low voltage has to be maintained for over 1ms in its original state, therefore there s a 1ms delay before entering the reset mode Rev. 1.90 HT82K94E/HT82K94A The LVR includes the following specifications: For a valid LVR signal, a low voltage i.e. a voltage in the range between 0.9V~V than 1ms ...
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... The device with remote wake-up function can wake-up the USB Host by sending a wake-up pulse through RMWK (bit 1 of the USC). Once the USB Host receives a wake-up signal from the HT82K94E/HT82K94A, it will send a Re- sume signal to the device. The timing is as follows: Configuring the Device as a PS2 Device ...
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... This bit is used to indicate that the current signal the USB is receiving from the Host is IN token. This bit is used to indicate that the SIE is transmitting NAK signal to the Host in re- NAK R sponse to the PC Host IN or OUT token. Rev. 1.90 HT82K94E/HT82K94A Bit 3 Bit 2 Pipe 3 Pipe 2 Pipe 3 Pipe 2 Pipe 3 Pipe 2 ...
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... After reading the current data, next data will show after 2 s, used to check the endpoint FIFO status and response to MISC register, if read/write action is still going on. Registers R/W FIFO0 R/W FIFO1 R/W FIFO2 R/W FIFO3 R/W Rev. 1.90 HT82K94E/HT82K94A Description SIES Function Function MISC (46H) Register Bank Address 1 48H 1 49H 1 4AH ...
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... PS2CKO W Data for driving the USBD+/CLK pin (Default Rev. 1.90 HT82K94E/HT82K94A MISC Setting Flow and Status 00H 01H delay 2 s, check 41H read* from FIFO0 register and check not ready (01H) 03H 02H 0AH 0BH delay 2 s, check 4BH write* to FIFO1 register and ...
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... Otherwise, the SIE cannot detect the USB signal. PS2_flag bit is only a bit for firmware to store the PS2 mode data. This bit only clear to zero by hardware after power-on reset. SUSPEND2 bit is used to second suspend mode. Rev. 1.90 HT82K94E/HT82K94A Function USR (1DH) Register 22 ...
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... PB0~PB7 wake-up enabled or disabled (by nibble) 14 PC0~PC7 wake-up enabled or disabled (by nibble) 15 PD0~PD7 wake-up enabled or disabled (by nibble) 16 TBHP enable or disable (default disable) 17 LVR/LVD kind: 2-battery or 3-battery Rev. 1.90 HT82K94E/HT82K94A Function SCC (1EH) Register Read/Write Option R/W Store current table read bit12~bit8 data Option 23 Functions April 29, 2008 ...
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... Application Circuits Crystal or Ceramic Resonator for Multiple I/O Applications - HT82K94E Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES high. X1 can use 6MHz or 12MHz close OSC1 & OSC2 as possible. ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.90 HT82K94E/HT82K94A Description 25 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. (5) : ROM code TBHP option is enabled (6) : ROM code TBHP option is disabled Rev. 1.90 HT82K94E/HT82K94A Description 26 Instruction Flag Cycle Affected 2 ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.90 PDF PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.90 PDF PDF PDF addr PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.90 PDF PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.90 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.90 Program Counter+1 PDF PDF PDF addr PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.90 PDF PDF Program Counter+1 PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.90 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.90 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.90 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.90 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.90 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT82K94E/HT82K94A April 29, 2008 ...
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... The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.90 PDF PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.90 PDF PDF PDF PDF HT82K94E/HT82K94A April 29, 2008 ...
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... Package Information 32-pin (5´5mm) SAW Type QFN Outline Dimensions Symbol Rev. 1.90 Dimensions in mm. Min. Nom. 0.7 0 0.2 0. 0.5 1.25 1.25 0.3 40 HT82K94E/HT82K94A Max. 0.8 0.05 0.3 3.25 3.25 0.5 April 29, 2008 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 1.90 Dimensions in mil Min. Nom. 395 291 8 613 HT82K94E/HT82K94A Max. 420 299 12 637 April 29, 2008 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.90 HT82K94E/HT82K94A Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 12.5+0.3 0.2 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 42 April 29, 2008 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.90 HT82K94E/HT82K94A Dimensions 0.3 8 0.1 1.75 0.1 5.5 0.05 1.5+0.1 1.5+0.25 4 0.1 2 0.05 5.25 0.1 5.25 0.1 1.1 0.1 0.3 0.05 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.90 HT82K94E/HT82K94A 44 April 29, 2008 ...