ht82k68e Holtek Semiconductor Inc., ht82k68e Datasheet
ht82k68e
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ht82k68e Summary of contents
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... EPROM 160 8 data RAM One external interrupt pin (shared with PC2) General Description The HT82K68E is an 8-bit high performance peripheral interface IC, designed for multiple I/O products and mul- timedia applications. It supports interface to a low speed PC with multimedia keyboard or wireless keyboard in Rev ...
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... Block Diagram Rev. 2.00 2 HT82K68E July 10, 2007 ...
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... Bidirectional 4-bit input/output port. Software* instructions determine the CMOS PC4~PC7 I/O or None output or Schmitt Trigger input with or without pull-high resistor. Pull-high Bidirectional 8-bit input/output port. Software* instructions determine the CMOS PD0~PD7 I/O or None output or Schmitt Trigger input with or without pull-high resistor. Rev. 2.00 Description 3 HT82K68E July 10, 2007 ...
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... Operating Temperature .......................... Test Conditions Min. V Conditions DD 2 load 6MHz SYS load 6MHz SYS load, system HALT load, system HALT 2.1 5V 3.5 4 HT82K68E Ta=25 C Typ. Max. Unit 5.5 V 0.7 1 0 ...
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... Test Conditions Min. V Conditions 4.8 OSC resistor 40k 5V 4.8 OSC resistor 40k Without WDT prescaler 5V 9 Without WDT prescaler 1 Power-up or wake-up from HALT 1 5 HT82K68E Typ. Max. Unit 0 100 150 ...
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... Functional Description Execution Flow The HT82K68E system clock is derived from either a crystal oscillator. The system clock is internally divided into four non-overlapping clocks. One instruc- tion cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle ...
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... Timer option Setting register (WDTS;09H), the Status reg- ister (STATUS;0AH), the Interrupt Control register Table Location P11~P8: Current program counter bits 7 HT82K68E 8 bits di July 10, 2007 ...
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... In addition, on entering an interrupt sequence or execut- ing a subroutine call, the status register will not be auto- matically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the sta- tus register, precaution must be taken to save it prop- erly. 8 HT82K68E July 10, 2007 ...
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... WDT time-out Unused bit, read as 0 Interrupt The HT82K68E provides an internal timer counter inter- rupt and an external interrupt shared with PC2. The in- terrupt control register (INTC;0BH) contains the interrupt control bits to set not only the enable/disable status but also the interrupt request flags. ...
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... Oscillator Configuration There are two oscillator circuits in HT82K68E. Both are designed for system clocks; the RC oscillator and the Crystal oscillator, which are determined by mask op- tions. No matter what oscillator type is selected, the signal provides the system clock ...
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... Once a wake-up event occurs, and the system clock co- mes from a crystal, it takes 1024 t riod) to resume normal operation. In other words, the HT82K68E will insert a dummy period after the wake-up. If the system clock comes from an RC oscilla- tor, it continues operating immediately. If the wake-up results in next instruction execution, this will execute im- mediately after the dummy period is completed ...
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... Points to the top of the stack Timer Counter A timer counter (TMR) is implemented in the HT82K68E. The timer counter contains an 8-bit pro- grammable count-up counter and the clock may come from the system clock divided by 4. Using the internal instruction clock, there is only one ref- erence time-base. There are two registers related to the timer counter ...
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... Timer Counter 13 HT82K68E WDT Time-out (HALT) (HALT) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 000H 000H uuuu uuuu ...
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... Input/Output Ports There are 32 bidirectional input/output lines in the HT82K68E, labeled from PA to PE, which are mapped to the data memory of [12H], [14H], [16H], [18H] and [1AH] respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H or 1AH) ...
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... Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. Rev. 2.00 The relationship between the voltage range for proper chip Note: OPR is shown be- operation at 4MHz system clock. Low Voltage Reset 15 HT82K68E and V is shown below. DD LVR July 10, 2007 ...
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... ROM Code Option The following shows six kinds of ROM code option in the HT82K68E. All the ROM code options must be defined to en- sure proper system function. No. OSC type selection. This option is to decide Crystal oscillator is chosen as system clock. If the 1 Crystal oscillator is selected, the XST (Crystal Start-up Timer) default is activated, otherwise the XST is dis- abled ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.00 Description 17 HT82K68E Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.00 Description 18 HT82K68E Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 2.00 PDF PDF PDF PDF PDF HT82K68E July 10, 2007 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 2.00 PDF PDF PDF addr PDF PDF HT82K68E July 10, 2007 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 2.00 PDF PDF PDF PDF PDF HT82K68E July 10, 2007 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 2.00 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT82K68E July 10, 2007 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 2.00 Program Counter+1 PDF PDF PDF addr PDF PDF HT82K68E July 10, 2007 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 2.00 PDF PDF Program Counter+1 PDF PDF PDF PDF HT82K68E July 10, 2007 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 2.00 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT82K68E July 10, 2007 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 2.00 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT82K68E July 10, 2007 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 2.00 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT82K68E July 10, 2007 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 2.00 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT82K68E July 10, 2007 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 2.00 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT82K68E July 10, 2007 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 2.00 PDF PDF PDF PDF PDF HT82K68E July 10, 2007 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 2.00 PDF PDF PDF HT82K68E July 10, 2007 ...
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... Package Information 20-pin SOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 394 290 14 490 HT82K68E Max. 419 300 20 510 104 July 10, 2007 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 394 290 14 697 HT82K68E Max. 419 300 20 713 104 July 10, 2007 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 2.00 Dimensions in mil Min. Nom. 395 291 8 613 HT82K68E Max. 420 299 12 637 July 10, 2007 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 35 HT82K68E July 10, 2007 ...
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... SSOP 48W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 Dimensions in mm 330 1.0 100 0.1 13.0+0.5 0.2 2.0 0.5 32.2+0.3 0.2 38.2 0.2 36 HT82K68E July 10, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 Dimensions in mm 24.0+0.3 0.1 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 37 HT82K68E July 10, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 38 HT82K68E July 10, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 39 HT82K68E July 10, 2007 ...