lcmxo2-2000ze-1uwg49itr1 Lattice Semiconductor Corp., lcmxo2-2000ze-1uwg49itr1 Datasheet
lcmxo2-2000ze-1uwg49itr1
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MachXO2™ Family Data Sheet Preliminary DS1035 Version 01.5, August 2011 ...
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... Programmable pull-up or pull-down mode © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Table 1-1. MachXO2™ Family Selection Guide XO2-256 LUTs 256 Distributed RAM (Kbits EBR SRAM (Kbits) Number of EBR SRAM 0 Blocks (9 Kbits/block) 0 UFM (Kbits) 2 ✓ HC Device Options ✓ ZE ...
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Lattice Semiconductor and oscillators dynamically. These features help manage static and dynamic power consumption resulting in low static power for all members of the family. The MachXO2 devices are available in two versions – ultra low power (ZE) and high ...
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... EBR blocks. © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor The logic blocks, Programmable Functional Unit (PFU) and sysMEM EBR blocks, are arranged in a two-dimen- sional grid with rows and columns. Each row has either the logic blocks or the EBR blocks. The PIO cells are located ...
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Lattice Semiconductor Slices Slices 0-3 contain two LUT4s feeding two registers. Slices 0-2 can be configured as distributed memory. Table 2-1 shows the capability of the slices in PFU blocks along with the operation modes they enable. In addition, each ...
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Lattice Semiconductor Table 2-2. Slice Signal Descriptions Function Type Input Data signal Input Data signal Input Multi-purpose Input Control signal Input Control signal Input Control signal Input Inter-PFU signal Output Data signals Output Data signals Output Data signals Output Data ...
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Lattice Semiconductor Ripple mode includes an optional configuration that performs arithmetic using fast carry chain methods. In this con- figuration (also referred to as CCU2 mode) two additional signals, Carry Generate and Carry Propagate, are gener- ated on a per-slice ...
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Lattice Semiconductor The eight primary clock lines in the primary clock network drive throughout the entire device and can provide clocks for all resources within the device including PFUs, EBRs and PICs. In addition to the primary clock signals, MachXO2 ...
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Lattice Semiconductor Eight secondary high fanout nets are generated from eight 8:1 muxes as shown in Figure 2-6. One of the eight inputs to the secondary high fanout net input mux comes from dual function clock pins and the remaining ...
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Lattice Semiconductor The LOCK signal is asserted when the PLL determines it has achieved lock and de-asserted if a loss of lock is detected. A block diagram of the PLL is shown in Figure 2-7. The setup and hold times ...
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Lattice Semiconductor Table 2-4 provides signal descriptions of the PLL block. Table 2-4. PLL Signal Descriptions Port Name I/O CLKI I CLKFB I PHASESEL[1:0] I PHASEDIR I PHASESTEP I CLKOP O CLKOS O CLKOS2 O CLKOS3 O LOCK O DPHSRC ...
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Lattice Semiconductor Table 2-5. sysMEM Block Configurations Single Port True Dual Port Pseudo Dual Port FIFO Bus Size Matching All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB word ...
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Lattice Semiconductor Figure 2-8. sysMEM Memory Primitives AD[12:0] DI[8:0] CLK CE OCE EBR DO[8:0] RST WE CS[2:0] Single-Port RAM DI[17:0] CLKW WE RST FULLI CSW[1:0] Table 2-6. EBR Signal Descriptions Port Name CLK Clock CE Clock Enable 1 OCE Output ...
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Lattice Semiconductor The EBR memory supports three forms of write behavior for single or dual port operation: 1. Normal – Data on the output appears only during the read cycle. During a write cycle, the data (at the current address) ...
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Lattice Semiconductor For further information on the sysMEM EBR block, please refer to TN1201, Devices. EBR Asynchronous Reset EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before ...
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Lattice Semiconductor Figure 2-11. Group of Four Programmable I/O Cells 1 PIC Core Logic/ Routing Notes: 1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices. 2. Output gearbox is available only ...
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Lattice Semiconductor PIO The PIO contains three blocks: an input register block, output register block and tri-state register block. These blocks contain registers for operating in a variety of modes along with the necessary clock and selection logic. Table 2-8. ...
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Lattice Semiconductor Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges) Programmable D Delay Cell SCLK Right Edge The input register block on the right edge is a superset of the same block on the ...
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Lattice Semiconductor In DDR generic mode, D0 and D1 inputs are fed into registers on the positive edge of the clock. At the next falling edge the registered D1 input is registered into the register Q1. A multiplexer running off ...
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Lattice Semiconductor Figure 2-15. MachXO2 Output Register Block Diagram (PIO on the Right Edges SCLK DQSW90 TD Tri-state Register Block The tri-state register block registers tri-state control signals from the core of the device before they are passed ...
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Lattice Semiconductor These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control ...
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Lattice Semiconductor More information on the input gearbox is available in TN1203, Devices. Output Gearbox Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or ...
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Lattice Semiconductor Figure 2-17. Output Gearbox ODDRx2_C CDN ODDRx2_A ODDRx2_C SCLK SEL /0 UPDATE ECLK0/1 More information on ...
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Lattice Semiconductor Block, to facilitate the generation of clock and control signals (DQSR90, DQSW90, DDRCLKPOL and DATAVALID). These clock and control signals are distributed to the other PIO in the group through dedicated low skew routing. DQS Read Write Block ...
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Lattice Semiconductor and differential input termination. The PCI clamp is enabled after V and the device has been configured. 3. Top sysIO Buffer Pairs The sysIO buffer pairs in the top bank of the device consist of two single-ended output ...
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Lattice Semiconductor Single-ended buffers with Types of Output Buffers complementary outputs (all I/O banks) Differential Output Emulation All I/O banks Capability PCI Clamp Support No Table 2-12. Supported Input Standards Input Standard Single-Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 ...
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Lattice Semiconductor Table 2-13. Supported Output Standards Output Standard Single-Ended Interfaces LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 LVCMOS33, Open Drain LVCMOS25, Open Drain LVCMOS18, Open Drain LVCMOS15, Open Drain LVCMOS12, Open Drain PCI33 SSTL25 (Class I) SSTL18 (Class I) HSTL18(Class ...
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Lattice Semiconductor Figure 2-18. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000 and MachXO2-7000 Banks VCCIO5 GND VCCIO4 GND VCCIO3 GND Figure 2-19. MachXO2-256, MachXO2-640/U and MachXO2-1200 Banks VCCIO3 GND MachXO2 Family Data Sheet GND VCCIO0 Bank 0 VCCIO1 GND Bank 2 GND VCCIO2 GND ...
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Lattice Semiconductor Hot Socketing The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power- down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of the ...
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Lattice Semiconductor Figure 2-20. Embedded Function Block Interface Core Logic/ Routing 2 Hardened Core Every MachXO2 device contains two I two cores can be configured either cores is that the primary core has pre-assigned ...
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Lattice Semiconductor 2 Figure 2-21 Core Block Diagram Core Logic/ Routing Table 2-15 describes the signals interfacing with the I 2 Table 2-15 Core Signal Description Signal Name I/O Bi-directional clock line of the I mode. ...
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Lattice Semiconductor There are some limitations on the use of the hardened user SPI. These are defined in the following technical notes: • TN1087, Minimizing System Interruption During Configuration Using TransFR Technology • TN1205, Using User Flash Memory and Hardened ...
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Lattice Semiconductor • Supports the following modes of operation: – Watchdog timer – Clear timer on compare match – Fast PWM – Phase and Frequency Correct PWM • Programmable clock input source • Programmable input clock prescaler • One static ...
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Lattice Semiconductor User Flash Memory (UFM) MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of applications including storing a portion of the configuration image, initializing EBRs, to store PROM data ...
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Lattice Semiconductor Table 2-18. MachXO2 Power Saving Features Description Device Subsystem Bandgap Power-On-Reset (POR) On-Chip Oscillator PLL I/O Bank Controller Dynamic Clock Enable for Primary Clock Nets Power Guard For more details on the standby mode refer to TN1198, Power ...
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Lattice Semiconductor Configuration and Testing This section describes the configuration and testing features of the MachXO2 family. IEEE 1149.1-Compliant Boundary Scan Testability All MachXO2 devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access port ...
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Lattice Semiconductor For applications where security is important, the lack of an external bitstream provides a solution that is inherently more secure than SRAM-based FPGAs. This is further enhanced by device locking. MachXO2 devices contain security bits that, when set, ...
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... LCMXO2 ZE/HE (1.2V) document is required volts is permitted for a duration of <20ns. IHMAX 1 Parameter and V are both the same voltage, they must also be the same CCIO CC power supply on boards. CC Condition 3-1 Preliminary Data Sheet DS1035 LCMXO2 HC (2.5V/3.3V) Min. Max. Units 1.14 1.26 V 2.375 3.465 V 1.14 3.465 V ° ° ...
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Lattice Semiconductor Power-On-Reset Voltage Levels Symbol Power-On-Reset ramp up trip point (band gap based circuit V PORUP monitoring V CCINT Power-On-Reset ramp up trip point (band gap based circuit V PORUPEXT monitoring external V Power-On-Reset ramp down trip point (band ...
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Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Leakage I/O Active Pull-up Current PU I/O Active Pull-down I PD Current Bus Hold Low sustaining I BHLS current Bus Hold High ...
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... I DCBG I DCPOR I DCIOBANKCONTROLLER DC and Switching Characteristics Device LCMXO2-256ZE LCMXO2-640ZE LCMXO2-1200ZE LCMXO2-2000ZE LCMXO2-4000ZE LCMXO2-7000ZE 5 All devices Power Estimation and Management for MachXO2 Parameter Bandgap DC power contribution POR DC power contribution DC power contribution per I/O bank controller 3-4 MachXO2 Family Data Sheet 4 Typ. Units 16 µ ...
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... LCMXO2-1200UHC LCMXO2-2000HC LCMXO2-2000UHC LCMXO2-4000HC LCMXO2-7000HC LCMXO2-2000HE LCMXO2-4000HE LCMXO2-7000HE 5 All devices Power Estimation and Management for MachXO2 Device LCMXO2-256ZE LCMXO2-640ZE LCMXO2-1200ZE LCMXO2-2000ZE LCMXO2-4000ZE LCMXO2-7000ZE 6 All devices Power Estimation and Management for MachXO2 or GND and all outputs are tri-stated. 3-5 DC and Switching Characteristics MachXO2 Family Data Sheet 4 Typ ...
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... Does not include pull-up/pull-down. CCIO Device LCMXO2-256HC LCMXO2-640HC LCMXO2-640UHC LCMXO2-1200HC LCMXO2-1200UHC LCMXO2-2000HC LCMXO2-2000UHC LCMXO2-4000HC LCMXO2-7000HC LCMXO2-2000HE LCMXO2-2000UHE LCMXO2-4000HE LCMXO2-7000HE 6 All devices Power Estimation and Management for MachXO2 or GND and all outputs are tri-stated. 3-6 DC and Switching Characteristics MachXO2 Family Data Sheet Typ ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.135 LVCMOS 2.5 2.375 LVCMOS 1.8 1.71 LVCMOS 1.5 1.425 LVCMOS 1.2 1.14 LVTTL 3.135 3 PCI 3.135 SSTL25 2.375 SSTL18 1.71 HSTL18 1. LVDS25 2.375 1, 2 ...
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Lattice Semiconductor sysIO Single-Ended DC Electrical Characteristics V IL Input/Output 3 Standard Min. (V) Max. (V) LVCMOS 3.3 -0.3 LVTTL LVCMOS 2.5 -0.3 LVCMOS 1.8 -0.3 0.35V LVCMOS 1.5 -0.3 0.35V LVCMOS 1.2 -0.3 0.35V PCI -0.3 0.3V SSTL25 Class ...
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Lattice Semiconductor sysIO Differential Electrical Characteristics The LVDS differential output buffers are available on the top side of MachXO2-640U, MachXO2-1200/U and higher density devices in the MachXO2 PLD family. LVDS Parameter Symbol Parameter Description Input Voltage INP ...
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Lattice Semiconductor LVDS Emulation MachXO2 devices can support LVDS outputs via emulation (LVDS25E). The output is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is ...
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Lattice Semiconductor BLVDS The MachXO2 family supports the BLVDS standard through emulation. The output is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs. The input standard is supported by the LVDS differential input buffer. ...
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Lattice Semiconductor LVPECL The MachXO2 family supports the differential LVPECL standard through emulation. This output standard is emu- lated using complementary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The LVPECL input standard is ...
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Lattice Semiconductor RSDS The MachXO2 family supports the differential RSDS standard. The output standard is emulated using complemen- tary LVCMOS outputs in conjunction with resistors across the driver outputs on all the devices. The RSDS input standard is supported by ...
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Lattice Semiconductor Typical Building Block Function Performance – HC/HE Devices Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions ...
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Lattice Semiconductor Typical Building Block Function Performance – ZE Devices Pin-to-Pin Performance (LVCMOS25 12mA Drive) Function Basic Functions 16-bit decoder 4:1 MUX 16:1 MUX Register-to-Register Performance Function Basic Functions 16:1 MUX 16-bit adder 16-bit counter 64-bit counter Embedded Memory Functions ...
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Lattice Semiconductor MachXO2 External Switching Characteristics – HC/HE Devices Parameter Description Clocks Primary Clocks Frequency for Primary Clock 8 f MAX_PRI Tree Clock Pulse Width for Primary t W_PRI Clock Primary Clock Skew Within a t SKEW_PRI Device Edge Clock ...
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Lattice Semiconductor Parameter Description Clock to Data Setup - PIO t Input Register with Data Input SU_DEL Delay Clock to Data Hold - PIO Input t H_DEL Register with Input Data Delay Clock Frequency of I/O and f MAX_IO PFU ...
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Lattice Semiconductor Parameter Description Clock to Data Hold - PIO Input t HPLL Register Clock to Data Setup - PIO t Input Register with Data Input SU_DELPLL Delay Clock to Data Hold - PIO Input t H_DELPLL Register with Input ...
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Lattice Semiconductor Parameter Description Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Aligned t Input Data Valid After ECLK DVA t Input Data Hold After ECLK DVE DDRX4 Serial Input Data ...
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Lattice Semiconductor Parameter Description Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered Output Data Valid Before CLK t DVB Output Output Data Valid After CLK t DVA Output DDRX2 Serial ...
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Lattice Semiconductor Parameter Description 9 LPDDR Input Data Valid After DQS t DVADQ Input Input Data Hold After DQS t DVEDQ Input Output Data Invalid Before t DQVBS DQS Output Output Data Invalid After DQS t DQVAS Output MEM LPDDR ...
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Lattice Semiconductor MachXO2 External Switching Characteristics – ZE Devices Parameter Description Clocks Primary Clocks Frequency for Primary Clock 8 f MAX_PRI Tree Clock Pulse Width for Primary t W_PRI Clock Primary Clock Skew Within a t SKEW_PRI Device Edge Clock ...
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Lattice Semiconductor Parameter Description Clock to Data Setup - PIO t Input Register with Data Input SU_DEL Delay Clock to Data Hold - PIO Input t H_DEL Register with Input Data Delay Clock Frequency of I/O and f MAX_IO PFU ...
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Lattice Semiconductor Parameter Description Clock to Data Hold - PIO Input t HPLL Register Clock to Data Setup - PIO t Input Register with Data Input SU_DELPLL Delay Clock to Data Hold - PIO Input t H_DELPLL Register with Input ...
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Lattice Semiconductor Parameter Description Generic DDR4 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input - GDDRX4_RX.ECLK.Aligned t Input Data Valid After ECLK DVA t Input Data Hold After ECLK DVE DDRX4 Serial Input Data ...
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Lattice Semiconductor Parameter Description Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered Output Data Valid Before CLK t DVB Output Output Data Valid After CLK t DVA Output DDRX2 Serial ...
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Lattice Semiconductor Parameter Description 9 LPDDR Input Data Valid After DQS t DVADQ Input Input Data Hold After DQS t DVEDQ Input Output Data Invalid Before t DQVBS DQS Output Output Data Invalid After DQS t DQVAS Output MEM LPDDR ...
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Lattice Semiconductor Figure 3-5. Receiver RX.CLK.Aligned and MEM DDR Input Waveforms RX CLK Input or DQS Input RX Data Input or DQ Input RX.Aligned Figure 3-6. Receiver RX.CLK.Centered Waveforms RX CLK Input RX Data Input RX.Centered Figure 3-7. Transmitter TX.CLK.Aligned ...
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Lattice Semiconductor Figure 3-9. GDDR71 Video Timing Waveforms 756 Mbps Clock In 125 MHz Data Out 756 Mbps Clock Out 125 MHz Figure 3-10. Receiver GDDR71_RX. Waveforms 0 t DVA t DVE Figure 3-11. Transmitter GDDR71_TX. Waveforms 0 t DIA ...
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Lattice Semiconductor sysCLOCK PLL Timing Parameter Descriptions f Input Clock Frequency (CLKI, CLKFB) IN Output Clock Frequency (CLKOP, CLKOS, f OUT CLKOS2) f Output Frequency (CLKOS3) OUT2 f PLL VCO Frequency VCO f Phase Detector Input Frequency PFD AC Characteristics ...
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... STANDBY DC and Switching Characteristics Parameter Device All LCMXO2-256 LCMXO2-640 LCMXO2-1200 LCMXO2-2000 LCMXO2-4000 LCMXO2-7000 All All Device All LCMXO2-256 LCMXO2-640 LCMXO2-640U LCMXO2-1200 LCMXO2-1200U LCMXO2-2000 LCMXO2-2000U LCMXO2-4000 LCMXO2-7000 All STANDBY Mode t PWRDN t WSTDBY 3-31 MachXO2 Family Data Sheet Min. Typ. Max 125.685 133 140.315 124 ...
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... BSCAN test update register, falling edge of clock to valid disable BTUODIS t BSCAN test update register, falling edge of clock to valid enable BTUPOEN DC and Switching Characteristics Parameter Device LCMXO2-256 LCMXO2-640 LCMXO2-640U LCMXO2-1200 LCMXO2-1200U LCMXO2-2000 LCMXO2-2000U LCMXO2-4000 LCMXO2-7000 Parameter 3-32 MachXO2 Family Data Sheet Typ. Units 507 µs 722 µs 722 µs 722 µ ...
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Lattice Semiconductor Figure 3-12. JTAG Port Timing Waveforms TMS TDI t BTCPH TCK TDO Data to be captured from I/O Data to be driven out to I/O DC and Switching Characteristics t t BTS BTH t BTCPL t t BTCO ...
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Lattice Semiconductor sysCONFIG Port Timing Specifications Symbol All Configuration Modes t PRGM t PRGMJ t INITL t DPPINIT t DPPDONE t IODISS Slave SPI f MAX t CCLKH t CCLKL t STSU t STH t STCO t STOZ t STOV ...
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Lattice Semiconductor Switching Test Conditions Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt- age, and other test conditions are shown in Table 3-5. Figure 3-13. Output Test Load, LVTTL and ...
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... Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Signal Name I/O General Purpose Input Configuration Clock for configuring an FPGA in Slave SPI mode. Output Configuration MCLK/CCLK I/O Clock for configuring an FPGA in SPI and SPIm configuration modes Slave SPI active low chip ...
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Lattice Semiconductor Pin Information Summary General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 ...
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Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank ...
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Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single-Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 ...
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Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank ...
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Lattice Semiconductor General Purpose I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Total General Purpose Single Ended I/O Differential I/O per Bank Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank ...
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Lattice Semiconductor For Further Information For further information regarding logic signal connections for various packages please refer to the MachXO2 Device Pinout Files. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the ...
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... August 2011 MachXO2 Part Number Description LCMXO2 – XXXX – X XXXXXX Device Family MachXO2 PLD Logic Capacity 256 = 256 LUTs 640 = 640 LUTs 1200 = 1280 LUTs 2000 = 2112 LUTs 4000 = 4320 LUTs 7000 = 6864 LUTs I/O Count Blank = Standard Device ...
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... LCMXO2-256ZE-2UMG64C LCMXO2-256ZE-3UMG64C LCMXO2-256ZE-1MG132C LCMXO2-256ZE-2MG132C LCMXO2-256ZE-3MG132C Part Number LCMXO2-640ZE-1TG100C LCMXO2-640ZE-2TG100C LCMXO2-640ZE-3TG100C LCMXO2-640ZE-1MG132C LCMXO2-640ZE-2MG132C LCMXO2-640ZE-3MG132C Part Number LCMXO2-1200ZE-1TG100C LCMXO2-1200ZE-2TG100C LCMXO2-1200ZE-3TG100C LCMXO2-1200ZE-1TG144C LCMXO2-1200ZE-2TG144C LCMXO2-1200ZE-3TG144C LCMXO2-1200ZE-1MG132C LCMXO2-1200ZE-2MG132C LCMXO2-1200ZE-3MG132C Part Number LCMXO2-2000ZE-1TG100C LCMXO2-2000ZE-2TG100C LCMXO2-2000ZE-3TG100C LCMXO2-2000ZE-1TG144C LCMXO2-2000ZE-2TG144C LCMXO2-2000ZE-3TG144C LCMXO2-2000ZE-1MG132C LCMXO2-2000ZE-2MG132C LCMXO2-2000ZE-3MG132C LUTs Supply Voltage Grade 256 1.2V -1 256 1.2V ...
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... LCMXO2-4000ZE-1TG144C LCMXO2-4000ZE-2TG144C LCMXO2-4000ZE-3TG144C LCMXO2-4000ZE-1MG132C LCMXO2-4000ZE-2MG132C LCMXO2-4000ZE-3MG132C LCMXO2-4000ZE-1BG256C LCMXO2-4000ZE-2BG256C LCMXO2-4000ZE-3BG256C LCMXO2-4000ZE-1FTG256C LCMXO2-4000ZE-2FTG256C LCMXO2-4000ZE-3FTG256C LCMXO2-4000ZE-1BG332C LCMXO2-4000ZE-2BG332C LCMXO2-4000ZE-3BG332C LCMXO2-4000ZE-1FG484C LCMXO2-4000ZE-2FG484C LCMXO2-4000ZE-3FG484C Part Number LCMXO2-7000ZE-1TG144C LCMXO2-7000ZE-2TG144C LCMXO2-7000ZE-3TG144C LCMXO2-7000ZE-1BG256C LCMXO2-7000ZE-2BG256C LCMXO2-7000ZE-3BG256C LCMXO2-7000ZE-1FTG256C LCMXO2-7000ZE-2FTG256C LCMXO2-7000ZE-3FTG256C LCMXO2-7000ZE-1BG332C LCMXO2-7000ZE-2BG332C LCMXO2-7000ZE-3BG332C LCMXO2-7000ZE-1FG484C LCMXO2-7000ZE-2FG484C LCMXO2-7000ZE-3FG484C LUTs Supply Voltage Grade 2112 1.2V -1 2112 1.2V ...
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... LCMXO2-1200ZE-1MG132CR1 1 LCMXO2-1200ZE-2MG132CR1 1 LCMXO2-1200ZE-3MG132CR1 1. Specifications for the “LCMXO2-1200ZE-speed package CR1” are the same as the “LCMXO2-1200ZE-speed package C” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Commercial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging Part Number LCMXO2-256HC-4TG100C ...
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... LCMXO2-1200HC-6TG100C LCMXO2-1200HC-4TG144C LCMXO2-1200HC-5TG144C LCMXO2-1200HC-6TG144C LCMXO2-1200HC-4MG132C LCMXO2-1200HC-5MG132C LCMXO2-1200HC-6MG132C Part Number LCMXO2-1200UHC-4FTG256C LCMXO2-1200UHC-5FTG256C LCMXO2-1200UHC-6FTG256C Part Number LCMXO2-2000HC-4TG100C LCMXO2-2000HC-5TG100C LCMXO2-2000HC-6TG100C LCMXO2-2000HC-4TG144C LCMXO2-2000HC-5TG144C LCMXO2-2000HC-6TG144C LCMXO2-2000HC-4MG132C LCMXO2-2000HC-5MG132C LCMXO2-2000HC-6MG132C LCMXO2-2000HC-4BG256C LCMXO2-2000HC-5BG256C LCMXO2-2000HC-6BG256C LCMXO2-2000HC-4FTG256C LCMXO2-2000HC-5FTG256C LCMXO2-2000HC-6FTG256C Part Number LCMXO2-2000UHC-4FG484C LCMXO2-2000UHC-5FG484C LCMXO2-2000UHC-6FG484C LUTs Supply Voltage Grade 1280 2.5V/3.3V -4 1280 2.5V/3.3V -5 1280 2 ...
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... LCMXO2-4000HC-5TG144C LCMXO2-4000HC-6TG144C LCMXO2-4000HC-4MG132C LCMXO2-4000HC-5MG132C LCMXO2-4000HC-6MG132C LCMXO2-4000HC-4BG256C LCMXO2-4000HC-5BG256C LCMXO2-4000HC-6BG256C LCMXO2-4000HC-4FTG256C LCMXO2-4000HC-5FTG256C LCMXO2-4000HC-6FTG256C LCMXO2-4000HC-4BG332C LCMXO2-4000HC-5BG332C LCMXO2-4000HC-6BG332C LCMXO2-4000HC-4FG484C LCMXO2-4000HC-5FG484C LCMXO2-4000HC-6FG484C Part Number LCMXO2-7000HC-4TG144C LCMXO2-7000HC-5TG144C LCMXO2-7000HC-6TG144C LCMXO2-7000HC-4BG256C LCMXO2-7000HC-5BG256C LCMXO2-7000HC-6BG256C LCMXO2-7000HC-4FTG256C LCMXO2-7000HC-5FTG256C LCMXO2-7000HC-6FTG256C LCMXO2-7000HC-4BG332C LCMXO2-7000HC-5BG332C LCMXO2-7000HC-6BG332C LCMXO2-7000HC-4FG484C LCMXO2-7000HC-5FG484C LCMXO2-7000HC-6FG484C LUTs Supply Voltage Grade 4320 2.5V/3.3V -4 4320 2.5V/3.3V -5 4320 2.5V/3.3V ...
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... LCMXO2-1200HC-4MG132CR1 1 LCMXO2-1200HC-5MG132CR1 1 LCMXO2-1200HC-6MG132CR1 1. Specifications for the “LCMXO2-1200HC-speed package CR1” are the same as the “LCMXO2-1200HC-speed package C” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Commercial Grade Devices without Voltage Regulator, Halogen Free (RoHS) Packaging Part Number LCMXO2-2000HE-4TG100C ...
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... LCMXO2-4000HE-4FG484C LCMXO2-4000HE-5FG484C LCMXO2-4000HE-6FG484C Part Number LCMXO2-7000HE-4TG144C LCMXO2-7000HE-5TG144C LCMXO2-7000HE-6TG144C LCMXO2-7000HE-4BG256C LCMXO2-7000HE-5BG256C LCMXO2-7000HE-6BG256C LCMXO2-7000HE-4FTG256C LCMXO2-7000HE-5FTG256C LCMXO2-7000HE-6FTG256C LCMXO2-7000HE-4BG332C LCMXO2-7000HE-5BG332C LCMXO2-7000HE-6BG332C LCMXO2-7000HE-4FG484C LCMXO2-7000HE-5FG484C LCMXO2-7000HE-6FG484C Ultra Low Power Industrial Grade Devices, Halogen Free (RoHS) Packaging Part Number LCMXO2-256ZE-1TG100I LCMXO2-256ZE-2TG100I LCMXO2-256ZE-3TG100I LCMXO2-256ZE-1UMG64I LCMXO2-256ZE-2UMG64I LCMXO2-256ZE-3UMG64I LCMXO2-256ZE-1MG132I LCMXO2-256ZE-2MG132I LCMXO2-256ZE-3MG132I ...
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... LCMXO2-2000ZE-3FTG256I 1. Samples can be ordered in minimum order quantities and increments of 50 units. Production volumes can be ordered in minimum order quantities and increments of 10,000 units for the LCMXO2-1200ZE in the 25-ball WLCSP package and 6,300 units for the LCMXO2- 2000ZE in the 49-ball WLCSP package. LUTs ...
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... LCMXO2-4000ZE-2TG144I LCMXO2-4000ZE-3TG144I LCMXO2-4000ZE-1MG132I LCMXO2-4000ZE-2MG132I LCMXO2-4000ZE-3MG132I LCMXO2-4000ZE-1BG256I LCMXO2-4000ZE-2BG256I LCMXO2-4000ZE-3BG256I LCMXO2-4000ZE-1FTG256I LCMXO2-4000ZE-2FTG256I LCMXO2-4000ZE-3FTG256I LCMXO2-4000ZE-1BG332I LCMXO2-4000ZE-2BG332I LCMXO2-4000ZE-3BG332I LCMXO2-4000ZE-1FG484I LCMXO2-4000ZE-2FG484I LCMXO2-4000ZE-3FG484I Part Number LCMXO2-7000ZE-1TG144I LCMXO2-7000ZE-2TG144I LCMXO2-7000ZE-3TG144I LCMXO2-7000ZE-1BG256I LCMXO2-7000ZE-2BG256I LCMXO2-7000ZE-3BG256I LCMXO2-7000ZE-1FTG256I LCMXO2-7000ZE-2FTG256I LCMXO2-7000ZE-3FTG256I LCMXO2-7000ZE-1BG332I LCMXO2-7000ZE-2BG332I LCMXO2-7000ZE-3BG332I LCMXO2-7000ZE-1FG484I LCMXO2-7000ZE-2FG484I LCMXO2-7000ZE-3FG484I LUTs Supply Voltage Grade 4320 1.2V -1 4320 1.2V -2 4320 1.2V ...
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... LCMXO2-1200ZE-1MG132IR1 1 LCMXO2-1200ZE-2MG132IR1 1 LCMXO2-1200ZE-3MG132IR1 1. Specifications for the “LCMXO2-1200ZE-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High-Performance Industrial Grade Devices with Voltage Regulator, Halogen Free (RoHS) Packaging Part Number LCMXO2-256HC-4TG100I ...
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... LCMXO2-1200HC-5TG144I LCMXO2-1200HC-6TG144I LCMXO2-1200HC-4MG132I LCMXO2-1200HC-5MG132I LCMXO2-1200HC-6MG132I Part Number LCMXO2-1200UHC-4FTG256I LCMXO2-1200UHC-5FTG256I LCMXO2-1200UHC-6FTG256I Part Number LCMXO2-2000HC-4TG100I LCMXO2-2000HC-5TG100I LCMXO2-2000HC-6TG100I LCMXO2-2000HC-4TG144I LCMXO2-2000HC-5TG144I LCMXO2-2000HC-6TG144I LCMXO2-2000HC-4MG132I LCMXO2-2000HC-5MG132I LCMXO2-2000HC-6MG132I LCMXO2-2000HC-4BG256I LCMXO2-2000HC-5BG256I LCMXO2-2000HC-6BG256I LCMXO2-2000HC-4FTG256I LCMXO2-2000HC-5FTG256I LCMXO2-2000HC-6FTG256I Part Number LCMXO2-2000UHC-4FG484I LCMXO2-2000UHC-5FG484I LCMXO2-2000UHC-6FG484I Part Number LCMXO2-4000HC-4TG144I LCMXO2-4000HC-5TG144I LCMXO2-4000HC-6TG144I LCMXO2-4000HC-4MG132I 1280 2.5V/3.3V -5 1280 2.5V/3.3V -6 1280 2.5V/3.3V ...
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... Part Number LCMXO2-4000HC-5MG132I LCMXO2-4000HC-6MG132I LCMXO2-4000HC-4BG256I LCMXO2-4000HC-5BG256I LCMXO2-4000HC-6BG256I LCMXO2-4000HC-4FTG256I LCMXO2-4000HC-5FTG256I LCMXO2-4000HC-6FTG256I LCMXO2-4000HC-4BG332I LCMXO2-4000HC-5BG332I LCMXO2-4000HC-6BG332I LCMXO2-4000HC-4FG484I LCMXO2-4000HC-5FG484I LCMXO2-4000HC-6FG484I Part Number LCMXO2-7000HC-4TG144I LCMXO2-7000HC-5TG144I LCMXO2-7000HC-6TG144I LCMXO2-7000HC-4BG256I LCMXO2-7000HC-5BG256I LCMXO2-7000HC-6BG256I LCMXO2-7000HC-4FTG256I LCMXO2-7000HC-5FTG256I LCMXO2-7000HC-6FTG256I LCMXO2-7000HC-4BG332I LCMXO2-7000HC-5BG332I LCMXO2-7000HC-6BG332I LCMXO2-7000HC-4FG484I LCMXO2-7000HC-5FG484I LCMXO2-7000HC-6FG484I LUTs Supply Voltage Grade 4320 2.5V/3.3V -5 4320 2.5V/3.3V -6 4320 2.5V/3.3V -4 4320 2 ...
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... LCMXO2-1200HC-4MG132IR1 1 LCMXO2-1200HC-5MG132IR1 1 LCMXO2-1200HC-6MG132IR1 1. Specifications for the “LCMXO2-1200HC-speed package IR1” are the same as the “LCMXO2-1200ZE-speed package I” devices respec- tively, except as specified in the R1 Device Specifications section on page 5-15 High Performance Industrial Grade Devices Without Voltage Regulator, Halogen Free (RoHS) Packaging Part Number ...
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... LCMXO2-7000HE-5FG484I LCMXO2-7000HE-6FG484I R1 Device Specifications The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts except as listed below. For more details on the R1 to Standard migration refer to AN8086, from MachXO2-1200-R1 to Standard Non-R1) • The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be ...
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Lattice Semiconductor • The on-chip differential input termination resistor value is higher than intended approximately 200 as opposed to the intended 100 recommended to use external termination resistors for differential inputs. The on-chip termination resistors can ...
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... PCI: www.pcisig.com © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Characteristics Pinout Information © 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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Lattice Semiconductor Date Version August 2011 01.4 Architecture DC and Switching Characteristics Pinout Information Ordering Information Supplemental Information August 2011 01.5 DC and Switching Characteristics Ordering Information Section Updated information in Clock/Control Distribution Network and sys- CLOCK Phase Locked Loops ...