gal16vp8 Lattice Semiconductor Corp., gal16vp8 Datasheet
gal16vp8
Related parts for gal16vp8
gal16vp8 Summary of contents
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... Memory Address, Data and Control Circuits — DMA Control • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL16VP8, with 64 mA drive capability and 15 ns maximum propagation delay time is ideal for Bus and Memory control appli- cations. The GAL16VP8 is manufactured using Lattice ...
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... GAL16VP8 Ordering Information Commercial Grade Specifications Tpd (ns) Tsu (ns) Tco (ns) Icc (mA Part Number Description GAL16VP8B Device Name Speed (ns Low Power Power Ordering # 115 GAL16VP8B-15LP 115 GAL16VP8B-15LJ 115 GAL16VP8B-25LP 115 GAL16VP8B-25LJ _ XXXXXXXX Specifications GAL16VP8 Package 20-Pin Plastic DIP ...
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... These two global and 24 individual architecture bits define all possible con- figurations in a GAL16VP8. The information given on these archi- tecture bits is only to give a better understanding of the device. Compiler software will transparently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits ...
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... OE XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16VP8 Registered outputs have eight product terms per output. I/Os have seven product terms per output. The JEDEC fuse numbers, including the User Electronic Signa- ture (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page ...
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... ELECTRONIC SIGNATURE FUSES 2056, 2055, .... Byte7 Byte6 .... MSB LSB Specifications GAL16VP8 DIP and PLCC Package Pinouts 2128 PTD 2191 .... 2118, 2119 .... Byte1 Byte0 5 20 OLMC 19 XOR-2048 AC1-2120 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16VP8 All macrocells have seven product terms per output. One prod- uct term is used for programmable output enable control. Pins 1 and 10 are always available as data inputs into the AND array. ...
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... ELECTRONIC SIGNATURE FUSES 2056, 2055, .... Byte7 Byte6 .... MSB LSB Specifications GAL16VP8 DIP and PLCC Package Pinouts 2128 PTD 2191 .... 2118, 2119 .... Byte1 Byte0 7 20 OLMC 19 XOR-2048 AC1-2120 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16VP8 Pins 1 and 10 are always available as data inputs into the AND array. The center two macrocells (pins 14 & 16) cannot be used in the input configuration. ...
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... ELECTRONIC SIGNATURE FUSES 2056, 2055, .... Byte7 Byte6 .... MSB DIP and PLCC Package Pinouts 2128 PTD 2191 .... 2118, 2119 .... Byte1 Byte0 LSB 9 Specifications GAL16VP8 20 OLMC XOR-2048 19 AC1-2120 AC2-2194 OLMC XOR-2049 AC1-2121 18 AC2-2195 OLMC XOR-2050 17 AC1-2122 AC2-2196 OLMC XOR-2051 ...
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... IL 3. MAX. Vin = MAX. Vin = 0.5V CC OUT = 0. 3. 15MHz Outputs Open = Specifications GAL16VP8 ) ............................... MIN. TYP. 4 — Vss – 0.5 2.0 — — — — — — — — 2.4 — IH — ...
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... Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL16VP8 Over Recommended Operating Conditions MAXIMUM* UNITS COM COM -15 -25 MIN. MAX. MIN. ...
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... Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL16VP8 INPUT or I/O FEEDBACK CLK VALID INPUT t REGISTERED pd OUTPUT REGISTERED OUTPUT CLK t wl REGISTERED FEEDBACK 12 VALID INPUT ...
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... UNDER TEST 500 50pF 500 50pF 500 50pF 500 5pF 500 5pF *C 13 Specifications GAL16VP8 CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su calculated value, derived by sub from the period of fmax w/internal ...
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... This provides a typical hysteresis of 200mV between positive and negative transitions of the inputs. High Drive Outputs All eight outputs of the GAL16VP8 are capable of driving 64 mA loads when driving low and 32 mA loads when driving high. Near symmetrical high and low output drive capability provides small skews between high-to-low and low-to-high output transitions ...
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... Power-Up Reset INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL16VP8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- t puts set low after a specified time ( pr MAX result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins ...
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... Temperature (deg. C) Delta Tpd Outputs 0 -0.1 -0.2 -0.3 -0.4 -0 Number of Outputs Switching Delta Tpd vs Output Loading Specifications GAL16VP8 Normalized Tco vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 Supply Voltage (V) Normalized Tco vs Temp 1.3 RISE 1.2 FALL 1.1 1 0.9 0.8 0.7 -55 - Temperature (deg. C) Switching 0 -0.25 -0.5 -0 ...
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... Delta Icc vs Vin (1 input) 3 2.5 2 1.5 1 0.5 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Voh vs Ioh 80.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 0.7 5.50 -55 - Temperature (deg. C) Input Clamp (Vik -2.00 -1.50 -1.00 -0.50 Vik (V) 17 Specifications GAL16VP8 Voh vs Ioh 4.5 4.25 4 3.75 3.5 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. 1.40 1.30 1.20 1.10 1.00 0.90 100 125 Frequency (MHz) 0.00 3.00 4.00 75 100 ...