gal16lv8 Lattice Semiconductor Corp., gal16lv8 Datasheet
gal16lv8
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gal16lv8 Summary of contents
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... CMOS with Electrically Erasable (E High speed erase times (<100ms) allow the devices to be repro- grammed quickly and efficiently. The 3.3V GAL16LV8 uses the same industry standard 16V8 archi- tecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations. ...
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... GAL16LV8 Ordering Information Conventional Packaging Commercial Grade Specifications Lead-Free Packaging Commercial Grade Specifications ...
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... The following is a list of the PAL architectures that the GAL16LV8 can emulate. It also shows the OLMC mode under which the GAL16LV8 emulates the PAL architecture. ...
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... XOR OE XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16LV8 Dedicated input or output functions can be implemented as sub- sets of the I/O function. Registered outputs have eight product terms per output. I/Os have seven product terms per output. ...
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... PLCC Package Pinout 2128 PTD 2191 5 Specifications GAL16LV8 OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 OLMC 16 XOR-2051 AC1-2123 OLMC 15 XOR-2052 AC1-2124 OLMC 14 XOR-2053 AC1-2125 OLMC 13 XOR-2054 ...
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... De- XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16LV8 signs requiring eight I/Os can be implemented in the Registered mode. All macrocells have seven product terms per output. One product term is used for programmable output enable control ...
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... PLCC Package Pinout 2128 PTD 2191 7 Specifications GAL16LV8 OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 OLMC 16 XOR-2051 AC1-2123 OLMC 15 XOR-2052 AC1-2124 OLMC 14 XOR-2053 AC1-2125 OLMC 13 XOR-2054 ...
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... XOR XOR Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically. Specifications GAL16LV8 Pins 1 and 11 are always available as data inputs into the AND array. The center two macrocells (pins 15 & 16) cannot be used as input or I/O pins, and are only available as dedicated outputs. ...
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... Simple Mode Logic Diagram 1 0000 0224 2 0256 0480 3 0512 0736 4 0768 0992 5 1024 1248 6 1280 1504 7 1536 1760 8 1792 2016 9 Specifications GAL16LV8 PLCC Package Pinout 2128 PTD 2191 9 OLMC 19 XOR-2048 AC1-2120 OLMC 18 XOR-2049 AC1-2121 OLMC 17 XOR-2050 AC1-2122 ...
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... The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and T Specifications GAL16LV8D Recommended Operating Conditions (1) Commercial Devices: ...
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... Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (T = 25° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL16LV8D Over Recommended Operating Conditions TYPICAL UNITS COM COM -3 -5 MIN. MAX. MIN. MAX. ...
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... Supply Current f toggle 1) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2) Typical values are at Vcc = 3.3V and T Specifications GAL16LV8C Recommended Operating Conditions (1) Commercial Devices: Ambient Temperature (T Supply voltage (V with Respect to Ground ...
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... Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Capacitance (T = 25° 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O Specifications GAL16LV8C COM -7 MIN. MAX — — 0 — ...
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... Switching Waveforms INPUT or I/O FEEDBACK COMBINATIONAL OUTPUT Combinatorial Output INPUT or I/O FEEDBACK t dis COMBINATIONAL OUTPUT Input or I/O to Output Enable/Disable t wh CLK f 1/ max (w/o fb) Clock Width Specifications GAL16LV8 INPUT or I/O FEEDBACK CLK VALID INPUT REGISTERED t pd OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 14 VALID INPUT ...
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... The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. 15 Specifications GAL16LV8 CLK LOGIC ARRAY REGISTER t ...
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... GAL16LV8D: Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GAL16LV8D Output Load Conditions (see figure) Test Condition A B High Z to Active High at 1.9V High Z to Active Low at 1.0V C Active High to High Z at 1.9V Active Low to High ...
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... NOTE: The electronic signature is included in checksum calcula- tions. Changing the electronic signature will alter the checksum. Security Cell A security cell is provided in the GAL16LV8 devices to prevent un- authorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. ...
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... INTERNAL REGISTER Q - OUTPUT FEEDBACK/EXTERNAL OUTPUT REGISTER Circuitry within the GAL16LV8 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q t outputs set low after a specified time ( the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins ...
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... GAL16LV8D: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.1 PT H->L 1.05 PT L->H 1 0.95 0.9 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.1 -0.2 -0.3 -0 Number of Outputs Switching Delta Tpd vs Output Loading Output Loading (pF) ...
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... GAL16LV8D: Typical AC and DC Characteristic Diagrams Vol vs Iol 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 0.00 10.00 20.00 30.00 40.00 Iol (mA) Normalized Icc vs Vcc 1.10 1.05 1.00 0.95 0.90 0.85 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vin (V) Specifications GAL16LV8 Voh vs Ioh 3 2.5 2 1.5 1 0.5 0 0.00 5.00 10.00 15.00 20.00 25.00 Ioh(mA) Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Input Clamp (Vik) ...
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... GAL16LV8C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 PT H->L 1.1 PT L->H 1 0.9 0.8 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Normalized Tpd vs Temp 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0.05 0 -0.05 -0.1 -0.15 -0.2 -0.25 -0 Number of Outputs Switching Delta Tpd vs Output Loading 34 30 RISE 26 22 FALL ...
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... GAL16LV8C: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 0.8 0.6 0.4 0.2 0 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 Iol (mA) Normalized Icc vs Vcc 1.20 1.10 1.00 0.90 0.80 3.00 3.15 3.30 3.45 3.60 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 Vin (V) Specifications GAL16LV8 Voh vs Ioh 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 Ioh (mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 -55 - 100 125 Temperature (deg. C) Input Clamp (Vik) ...