gal20v8zd-15qp Lattice Semiconductor Corp., gal20v8zd-15qp Datasheet

gal20v8zd-15qp

Manufacturer Part Number

gal20v8zd-15qp

Description

Zero Power E2cmos Pld Gal

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL20V8ZD-15QP.pdf (19 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

GAL20V8ZD-15QP

Manufacturer:

LATTICE/莱迪斯

Quantity:

20 000

Current page: 1 of 19
Download datasheet (309Kb)

• ZERO POWER E

• HIGH PERFORMANCE E

• E

• EIGHT OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

The GAL20V8Z and GAL20V8ZD, at 100 A standby current and

12ns propagation delay provides the highest speed and lowest

power combination PLD available in the market. The

GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad-

vanced zero power E

Electrically Erasable (E

The GAL20V8Z uses Input Transition Detection (ITD) to put the

device in standby mode and is capable of emulating the full func-

tionality of the standard GAL20V8. The GAL20V8ZD utilizes a

dedicated power-down pin (DPP) to put the device in standby mode.

It has 19 inputs available to the AND array.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20v8zzd_03

Features

Description

— 100 A Standby Current

— Input Transition Detection on GAL20V8Z

— Dedicated Power-down Pin on GAL20V8ZD

— Input and Output Latching During Power Down

— 12 ns Maximum Propagation Delay

— Fmax = 83.3 MHz

— 8 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Output Drive

— UltraMOS

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Similar to Standard GAL20V8

— 100% Functional Testability

— Battery Powered Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

CELL TECHNOLOGY

Advanced CMOS Technology

CMOS TECHNOLOGY

CMOS process, which combines CMOS with

) floating gate technology.

CMOS TECHNOLOGY

Functional Block Diagram

Pin Configuration

I/DPP

N C

I/DPP

I/CLK

1 1

1 2

GAL20V8ZD

GAL20V8Z

Top View

1 4

PLCC

1 6

2 8

1 8

2 6

Zero Power E

2 5

2 3

2 1

1 9

GAL20V8ZD

I/O/Q

N C

I/O/Q

GAL20V8Z

I/D P P

I/C LK

G N D

1 2

IMUX

OLMC

IMUX

20V8ZD

20V8Z

December 1997

GAL

DIP

CMOS PLD

CLK

1 8

2 4

1 3

I/O/Q

I/OE

V c c

I/ O/ Q

I/O/Q

I/ O/ Q

I /O E

Related parts for gal20v8zd-15qp

gal20v8zd-15qp Summary of contents

Page 1

... High Speed Graphics Processing • ELECTRONIC SIGNATURE FOR IDENTIFICATION Description The GAL20V8Z and GAL20V8ZD, at 100 A standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad- ...

Page 2

... GAL20V8Z-15QP 55 100 GAL20V8Z-15QJ Icc (mA 100 GAL20V8ZD-12QP 55 100 GAL20V8ZD-12QJ 55 100 GAL20V8ZD-15QP 55 100 GAL20V8ZD-15QJ _ XXXXXXXX Specifications GAL20V8Z GAL20V8ZD Ordering # Package 24-Pin Plastic DIP 28-Lead PLCC 24-Pin Plastic DIP 28-Lead PLCC Ordering # Package 24-Pin Plastic DIP 28-Lead PLCC ...

Page 3

... When using the standard GAL20V8 JEDEC fuse pattern generated by the logic compilers for the GAL20V8ZD, special attention must be given to pin 4(5) (DPP) to make sure that it is not used as one of the functional inputs. ...

Page 4

... Specifications GAL20V8Z Registered outputs have eight product terms per output. I/Os have seven product terms per output. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers, including the User Electronic Signature (UES) fuses and the Product Term Disable (PTD) fuses, are shown on the logic diagram on the following page ...

Page 5

... PTD 2703 .... 2630, 2631 .... Byte1 Byte0 5 Specifications GAL20V8Z GAL20V8ZD 23(27) OLMC 22(26) XOR-2560 AC1-2632 OLMC 21(25) XOR-2561 AC1-2633 OLMC 20(24) XOR-2562 AC1-2634 OLMC 19(23) XOR-2563 AC1-2635 OLMC 18(21) XOR-2564 AC1-2636 OLMC 17(20) XOR-2565 AC1-2637 OLMC 16(19) XOR-2566 AC1-2638 OLMC 15(18) XOR-2567 AC1-2639 14(17) OE 13(16) SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...

Page 6

... All macrocells have seven product terms per output. One product term is used for programmable output enable control. Pins 1(2) and 13(16) are always available as data inputs into the AND array. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram on the following page ...

Page 7

... PTD 2703 .... 2630, 2631 .... Byte1 Byte0 7 GAL20V8ZD 23(27) OLMC 22(26) XOR-2560 AC1-2632 OLMC 21(25) XOR-2561 AC1-2633 OLMC 20(24) XOR-2562 AC1-2634 OLMC 19(23) XOR-2563 AC1-2635 OLMC 18(21) XOR-2564 AC1-2636 OLMC 17(20) XOR-2565 AC1-2637 OLMC 16(19) XOR-2566 AC1-2638 OLMC 15(18) XOR-2567 AC1-2639 14(17) 13(16) SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...

Page 8

... Pins 1(2) and 13(16) are always available as data inputs into the AND array. The center two macrocells (pins 18(21) & 19(23)) can- not be used in the input configuration. Pin 4(5) is used as dedicated power-down pin on GAL20V8ZD. It cannot be used as functional input. The JEDEC fuse numbers including the UES fuses and PTD fuses are shown on the logic diagram ...

Page 9

... Byte1 Byte0 9 GAL20V8ZD 2640 PTD 23(27) OLMC XOR-2560 22(26) AC1-2632 OLMC XOR-2561 21(25) AC1-2633 OLMC XOR-2562 20(24) AC1-2634 OLMC XOR-2563 19(23) AC1-2635 OLMC XOR-2564 18(21) AC1-2636 OLMC XOR-2565 17(20) AC1-2637 OLMC XOR-2566 16(19) AC1-2638 OLMC XOR-2567 15(18) AC1-2639 14(17) 13(16) 2703 SYN-2704 AC0-2705 * Note: Input not available on GAL20V8ZD ...

Page 10

... I = -100 A Vin = 0.5V CC OUT = GND V = Vcc Outputs Open 0. 3. MHz Outputs Open = MAXIMUM Specifications GAL20V8Z GAL20V8ZD ) ............................... MIN. TYP. 2 — Vss – 0.5 2.0 — — — — — — — 2.4 — Vcc-1 — ...

Page 11

... Standby Power Timing Waveforms Icc POWER Isb INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL20V8Z Specifications GAL20V8Z Over Recommended Operating Conditions en GAL20V8ZD COM COM -12 -15 MIN. MAX. MIN. MAX — 6 — — 15 — ...

Page 12

... C Input or I/O to Output Disabled Output Disabled 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Specifications GAL20V8Z Specifications GAL20V8ZD Over Recommended Operating Conditions 12 GAL20V8ZD COM COM -12 -15 UNITS MIN. MAX. ...

Page 13

... DPP Low to Valid Clock t dlov A DPP Low to Valid Output 1) Refer to Switching Test Conditions section. Dedicated Power-Down Pin Timing Waveforms DPP INPUT or I/O FEEDBACK OE CLK OUTPUT Specifications GAL20V8Z Specifications GAL20V8ZD Over Recommended Operating Conditions t t ivdh dhix t t gvdh dhgx t t cvdh dhcx ...

Page 14

... Clock Width INPUT or I/O FEEDBACK t pd CLK REGISTERED OUTPUT REGISTERED OUTPUT t wl CLK REGISTERED FEEDBACK 14 Specifications GAL20V8Z GAL20V8ZD VALID INPUT max (external fdbk) Registered Output t t dis Output Enable/Disable f 1/ max (internal fdbk ...

Page 15

... See Figure FROM OUTPUT (O/Q) UNDER TEST 390 50pF 390 50pF 390 50pF 390 5pF *C 390 5pF 15 Specifications GAL20V8Z GAL20V8ZD CLK LOGIC ARRAY REGISTER max with Internal Feedback 1/( su+ + INCLUDES TEST FIXTURE AND PROBE CAPACITANCE ...

Page 16

... Dedicated Power-Down Pin The GAL20V8ZD uses pin 4 (pin 5 on PLCC) as the dedicated power-down signal to put the device in power-down state. DPP is an active high signal where logic high driven on this signal puts the device into power-down state ...

Page 17

... The clock must also meet the minimum pulse width requirements. Vcc Vcc Data Output 17 Specifications GAL20V8Z GAL20V8ZD Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" ...

Page 18

... FALL - Number of Outputs Switching Delta Tco vs Output Loading 10 RISE 8 FALL 100 150 200 250 300 Specifications GAL20V8Z GAL20V8ZD Normalized Tsu vs Vcc 1.4 RISE 1.3 FALL 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.50 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 PT H->L 1.2 PT L->H 1.1 1 0.9 0.8 0.7 Temperature (deg. C) Switching RISE FALL ...

Page 19

... Normalized Icc vs Temp 1.2 1.1 1 0.9 0.8 5.50 -55 - Temperature (deg. C) Input Clamp (Vik -1.00 -0.80 -0.60 -0.40 -0.20 Vik (V) 19 Specifications GAL20V8Z GAL20V8ZD Voh vs Ioh 5 4.5 4 3.5 3 2.5 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. (DPP & ITD > 10MHz) 1.30 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) Normalized Icc vs Freq. (ITD) 1 0.8 0.6 0.4 0.2 0 ...

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