gal26cv12 Lattice Semiconductor Corp., gal26cv12 Datasheet

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gal26cv12

Manufacturer Part Number
gal26cv12
Description
High Performance E2 Cmos Pld Generic Array Logic? Gal26cv12 Gal
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• LOW POWER CMOS
• E
• TWELVE OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26CV12, at 7.5 ns maximum propagation delay time,
combines a high performance CMOS process with Electrically
Erasable (E
performance 28-pin PLD available on the market. E
offers high speed (<100ms) erase times, providing the ability to
reprogram or reconfigure the device quickly and efficiently.
Expanding upon the industry standard 22V10 architecture, the
GAL26CV12 eliminates the learning curve typically associated with
using a new device architecture. The generic architecture provides
maximum design flexibility by allowing the Output Logic Macrocell
(OLMC) to be configured by the user. The GAL26CV12 OLMC is
fully compatible with the OLMC in standard bipolar and CMOS
22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers100% field programmability and functionality
of all GAL products. In addition, 100 erase/write cycles and data
retention in excess of 20 years are specified.
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
26cv12_03
Features
Description
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Uses Standard 22V10 Macrocells
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
2
) floating gate technology to provide the highest
®
Advanced CMOS Technology
2
CMOS
®
TECHNOLOGY
2
technology
1
Functional Block Diagram
Pin Configuration
VCC
I
I
I
I
I
I
11
5
7
9
I/CLK
12
GAL26CV12
4
I
I
I
I
I
I
I
I
I
I
I
I
Top View
14
PLCC
2
High Performance E
16
28
18
26
25
23
21
19
GAL26CV12
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Generic Array Logic™
PRESET
10
12
12
10
8
8
8
8
8
8
8
8
RESET
I/CLK
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Vcc
I
I
I
I
I
I
I
I
I
I
I
I
1
7
14
26CV12
2
GAL
DIP
CMOS PLD
June 2000
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
INPUT
28
21
15
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q

Related parts for gal26cv12

gal26cv12 Summary of contents

Page 1

... GAL26CV12 eliminates the learning curve typically associated with using a new device architecture. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC configured by the user. The GAL26CV12 OLMC is fully compatible with the OLMC in standard bipolar and CMOS 22V10 devices. ...

Page 2

... GAL26CV12 Ordering Information Commercial Grade Specifications Industrial Grade Specifications ...

Page 3

... AND array, with both the true and complement of the feedback available as inputs to the AND array. Specifications GAL26CV12 The GAL26CV12 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two prod- uct terms are common to all registered OLMCs. The Asynchronous Reset sets all registered outputs to zero any time this dedicated product term is asserted ...

Page 4

... Registered Mode ACTIVE LOW Combinatorial Mode ACTIVE LOW Specifications GAL26CV12 ACTIVE HIGH ACTIVE HIGH ...

Page 5

... GAL26CV12 Logic Diagram/JEDEC Fuse Map 0000 0052 . . . 0468 2 0520 . . . 0936 3 0988 . . . 1404 4 1456 . . . 1872 5 1924 . . . . 2444 6 2496 . . . . . 3120 8 3172 . . . . . 3796 9 3848 . . . . 4368 10 4420 . . . 4836 11 4888 . . . 5304 12 5356 . . . 5772 13 5824 . . . 6240 14 6292 6368, 6369 ... Byte 7 Byte 6 Byte 5 Byte Specifications GAL26CV12 DIP & ...

Page 6

... The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL26CV12C Specifications GAL26CV12 Recommended Operating Conditions (1) Commercial Devices: +1.0V ...

Page 7

... Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL26CV12C Specifications GAL26CV12 Recovery Time Recovery Time MAXIMUM* UNITS COM IND -7 -10 MIN. MAX. MIN. MAX. ...

Page 8

... The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 5V and T Specifications GAL26CV12B Specifications GAL26CV12 Recommended Operating Conditions (1) Commercial Devices: +1.0V ...

Page 9

... Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. Capacitance ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications GAL26CV12B Specifications GAL26CV12 Over Recommended Operating Conditions MIN. MAX — 71.4 105 105 ...

Page 10

... OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING CLK REGISTERED OUTPUT Synchronous Preset Specifications GAL26CV12 INPUT or I/O FEEDBACK VALID INPUT t pd CLK REGISTERED OUTPUT t en CLK REGISTERED FEEDBACK INPUT or I/O FEEDB ACK DRIVI NG AR ...

Page 11

... Input Pulse Levels Input Rise and C-7/-10/-15 Fall Times B-10/-15/-20 Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GAL26CV12 Output Load Conditions (see figure) Test Condition 300 B Active High Active Low 300 ...

Page 12

... The signature data is always avail- able to the user independent of the state of the security cell. Security Cell A security cell is provided in every GAL26CV12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device ...

Page 13

... OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Circuitry within the GAL26CV12 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q outputs set low after a specified time (tpr MAX result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins ...

Page 14

... GAL26CV12C: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.25 -0.5 -0. Number of Outputs Switching Delta Tpd vs Output Loading 12 RISE 10 8 FALL 100 ...

Page 15

... GAL26CV12C: Typical AC and DC Characteristic Diagrams Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.3 1.2 1.1 1 0.9 0.8 0.7 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL26CV12 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) ...

Page 16

... GAL26CV12B: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0 Number of Outputs Switching Delta Tpd vs Output Loading Specifications GAL26CV12 Normalized Tco vs Vcc 1 ...

Page 17

... GAL26CV12B: Typical AC and DC Characteristic Diagrams Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 Supply Voltage (V) Delta Icc vs Vin (1 input 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications GAL26CV12 Voh vs Ioh 100.00 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 5.50 -55 - Temperature (deg. C) Input Clamp (Vik) ...

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