gal26v12 Lattice Semiconductor Corp., gal26v12 Datasheet

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gal26v12

Manufacturer Part Number
gal26v12
Description
High Performance E2 Cmos Pld Generic Array Logictm Gal26v12 Gal
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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• HIGH PERFORMANCE E
• LOW POWER CMOS
• E
• TWELVE OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL26V12, at 7.5ns maximum propagation delay time, com-
bines a high performance CMOS process with Electrically Eras-
able (E
ance available of any 26V12 device on the market. E
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL26V12 is fully function/fuse map/parametric
compatible with other 26V12 devices.
Unique test circuitry and reprogrammable cells allow complete
AC, DC, and functional testing during manufacture. As a result,
LATTICE is able to guarantee 100% field programmability and
functionality of all GAL
erase/rewrite cycles.
Copyright ©2000 Lattice Semiconductor Corp. GAL, E
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A.
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
FEATURES
— 7.5 ns Maximum Propagation Delay
— Fmax = 142.8 MHz
— 4.5 ns Maximum from Clock Input to Data Output
— TTL Compatible 16 mA Outputs
— UltraMOS
— 90 mA Typical Icc
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/Guaranteed 100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
DESCRIPTION
2
CELL TECHNOLOGY
2
) floating gate technology to provide the highest perform-
®
Advanced CMOS Technology
®
products. LATTICE also guarantees 100
2
CMOS
®
2
TECHNOLOGY
CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
2
technol-
VCC
INPUT/CLK 2
FUNCTIONAL BLOCK DIAGRAM
PACKAGE DIAGRAMS
I/CLK 1
I
I
I
I
I
I
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
11
5
7
9
12
4
GAL26V12
Top View
PLCC
14
2
High Performance E
16
28
18
26
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
Generic Array Logic
GAL26V12
RESET
PRESET
10
12
14
16
16
14
12
10
8
8
8
8
I/CLK1
I/CLK2
OLMC 10
OLMC 11
OLMC 4
OLMC 5
OLMC 0
OLMC 6
OLMC 7
OLMC 8
OLMC 9
OLMC 1
OLMC 2
OLMC 3
Vcc
I
I
I
I
I
I
I
I
I
I
I
November 2000
1
7
14
2
26V12
CMOS PLD
GAL
DIP
28
21
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
INPUT
I
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
GND
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TM

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gal26v12 Summary of contents

Page 1

... State Machine Control — High Speed Graphics Processing — Standard Logic Speed Upgrade • ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The GAL26V12, at 7.5ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Eras- 2 able (E ) floating gate technology to provide the highest perform- ance available of any 26V12 device on the market. E ogy offers high speed (< ...

Page 2

... XXXXXXXX Specifications GAL26V12 ...

Page 3

... GAL26V12 OUTPUT LOGIC MACROCELL (OLMC) OUTPUT LOGIC MACROCELL CONFIGURATIONS Each of the Macrocells of the GAL26V12 has two primary func- tional modes: registered, and combinatorial I/O. The modes and the output polarity are set by four architecture bits (S0, S1, S2 and S3), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page ...

Page 4

... ACTIVE LOW REGISTERED OUTPUT WITH I/O FEEDBACK Selects CLK1 Selects CLK2 Specifications GAL26V12 CLK1/ Q CLK2 S P ACTIVE HIGH REGISTERED OUTPUT WITH BURIED FEEDBACK Selects CLK1 Selects CLK2 ...

Page 5

... Selects CLK1 Selects CLK2 Specifications GAL26V12 ACTIVE HIGH COMBINATORIAL OUTPUT WITH I/O FEEDBACK Selects CLK1 Selects CLK2 CLK1/ Q CLK2 S P ACTIVE HIGH COMBINATORIAL OUTPUT WITH BURIED REGISTER FEEDBACK ...

Page 6

... GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP 0000 0052 . . . 0468 2 0520 . . . 0936 3 0988 . . . . 1508 4 1560 . . . . . 2184 5 2236 . . . . . . 2964 6 3016 . . . VCC . . 3848 Specifications GAL26V12 44 48 ASYNCH RESET OLMC 27 S0-7800 S1-7812 S2-7824 S3-7836 ...

Page 7

... GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP (CONT 3900 . . . . . . . 4732 9 4784 . . . . . . 5512 10 5564 . . . . . 6136 11 6188 . . . . 6760 12 6812 . . . 7228 13 7280 . . . 7696 14 7748 7848 7849... Electronic Signature ...7910 7911 ...

Page 8

... MAX. Vin = 0.5V CC OUT = 0. 3. 15MHz IL IH toggle = 0. 3. 15MHz IL IH toggle = Specifications GAL26V12C Specifications GAL26V12 ) ............................. ........................... – MIN. TYP. 4 — Vss – 0.5 2.0 — — — — — — — 2.4 — ...

Page 9

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. CAPACITANCE ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Guaranteed but not 100% tested. Specifications GAL26V12C Specifications GAL26V12 Over Recommended Operating Conditions -7 MIN. MAX. — 7.5 — 4.5 — — 5.5 — ...

Page 10

... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. CAPACITANCE ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Guaranteed but not 100% tested. Specifications GAL26V12C Specifications GAL26V12 Over Recommended Operating Conditions 105.2 125.0 MAXIMUM* UNITS Commercial -10 -15 -20 MIN. MAX. MIN. ...

Page 11

... CLK REGISTERED OUTPUT t en CLK REGISTERED FEEDBACK INPUT or I/O FEEDBACK DRIVING CLK REGISTERED OUTPUT 11 Specifications GAL26V12 VALID INPUT (external fdbk) Registered Output ...

Page 12

... L 390 50pF 390 50pF 390 50pF 390 5pF 390 5pF 12 Specifications GAL26V12 max with Internal Feedback 1/( Note: tcf is a calculated value, derived by sub- tracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu) ...

Page 13

... The signature data is always available to the user independent of the state of the security cell. SECURITY CELL A security cell is provided in every GAL26V12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device ...

Page 14

... POWER-UP RESET Circuitry within the GAL26V12 provides a reset signal to all reg- isters during power-up. All internal registers will have their Q out- puts set low after a specified time (tpr MAX result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins ...

Page 15

... Number of Outputs Switching Delta Tco vs Output Loading 12 RISE 10 8 FALL 150 200 250 300 0 50 100 Output Loading (pF) 15 Specifications GAL26V12 Normalized Tsu vs Vcc 1.2 1.1 1 0.9 0.8 5.50 4.50 4.75 5.00 Supply Voltage (V) Normalized Tsu vs Temp 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 125 -55 - Temperature (deg. C) Switching ...

Page 16

... Vin (V) Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 5.50 -55 - Temperature (deg. C) Input Clamp (Vik -2.00 -1.50 -1.00 -0.50 Vik (V) 16 Specifications GAL26V12 Voh vs Ioh 4 3.75 3.5 3.25 3 0.00 1.00 2.00 Ioh(mA) Normalized Icc vs Freq. 1.50 1.40 1.30 1.20 1.10 1.00 0.90 0.80 100 125 Frequency (MHz) 0.00 3.00 4.00 75 100 ...

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