m52d64322a Elite Semiconductor Memory Technology Inc., m52d64322a Datasheet
m52d64322a
Related parts for m52d64322a
m52d64322a Summary of contents
Page 1
... GENERAL DESCRIPTION The M52D64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized 524,288 words by 32 bits. Synchronous design allows precise cycle controls with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications ...
Page 2
... Data inputs / outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. M52D64322A Bank D Bank C Bank B Bank A ...
Page 3
... ≤ 3ns acceptable. ≤ 3ns acceptable all other pins are not under test = 0V. DDQ ≤ OUT DDQ = 25 C ° 1MHZ) SYMBOL C IN1 C IN2 C OUT M52D64322A VALUE -1.0 ~ 2.6 -1.0 ~ 2.6 -55 ~ +150 ° MAX UNIT 1 +0.3 V DDQ 0 0.2 V μ μ ...
Page 4
... CKE V (min), CLK V (max Input signals are stable I = 0mA, Page Burst OL All Band Activated, tCCD = tCCD (min) ≥ (min TCSR range ≤ CKE 0.2V ≤ CKE 0.2V M52D64322A C Version -10 45 0.5 ∞ = 0.3 =10ns 6.5 ∞ ∞ =15ns 40 ∞ ...
Page 5
... RFC t (min) CDL t (min) RDL t (min) BDL t (min) CCD t (min) MRD CAS latency=3 CAS latency=2 t (max) REF after self refresh exit. RFC M52D64322A Unit / 0 DDQ ns V DDQ Vtt =0.5x VDDQ 50 Z0= (Fig.2) AC Output Load Circuit Version Unit - ...
Page 6
... CAS Latency = CAS Latency =2 CAS Latency =3 t SAC CAS Latency = SLZ CAS Latency =3 t SHZ CAS Latency =2 *All AC parameters are measured from half to half. M52D64322A -10 Unit Note Min Max 10 1000 13.5 2 ...
Page 7
... X X Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M52D64322A DQM BA0 WE A9~A0 A10/AP BA1 CODE Row Address L Column ...
Page 8
... Reserved Reserved Reserved Reserved Reserved Reserved M52D64322A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
Page 9
... Elite Semiconductor Memory Technology Inc Address bus TCSR PASR Extended Mode Register Set DS M52D64322A A2-A0 Self Refresh Coverage 000 4Bank 001 2 Bank (BankA& BankB) or (BA1=0) PASR 010 1 Bank (BankA) or (BA0=BA1=0) 011 R 100 R 101 1/2 Bank (BankA) or ...
Page 10
... M52D64322A Interleave Interleave ...
Page 11
... CS high. CS high disables the command decoder so that RAS , CAS , WE and all the address inputs are ignored. Elite Semiconductor Memory Technology Inc. M52D64322A MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the ...
Page 12
... Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M52D64322A after the last data input to RDL is defined as the minimum number of clock RP ...
Page 13
... NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. with clock cycle RFC M52D64322A before the SDRAM RFC Publication Date: Jan. 2009 Revision: 1.4 13/46 ...
Page 14
... CAS WE BA1, BA0 = Low) The M52D64322A has a mode register that defines how the device operates. In this command, A0 through BA0 are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. During 2CLK ...
Page 15
... When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10 is Low, only the bank selected by BA1 and BA0 is precharged. After this command, the M52D64322A can’t accept the activate command to the precharging bank during t (precharge to activate command period). ...
Page 16
... CS , RAS , CAS , CKE = Low , WE = High) After the command execution, self refresh operation continues while CKE remains low. When CKE goes to high, the M52D64322A exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control ...
Page 17
... ESMT No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 17/46 ...
Page 18
... M52D64322A ...
Page 19
... M52D64322A ...
Page 20
... D Q Elite Semiconductor Memory Technology Inc M52D64322A D 3 Publication Date: Jan. 2009 Revision: 1.4 20/46 ...
Page 21
... M52D64322A Publication Date: Jan. 2009 Revision: 1.4 21/46 ...
Page 22
... M52D64322A ...
Page 23
... determinates the last data write. RDL min delay) with DQM. RAS M52D64322A * ...
Page 24
... from self refresh exit command, any other command can not be accepted. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 24/46 ...
Page 25
... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 25/46 ...
Page 26
... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52D64322A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: Jan. 2009 Revision: 1.4 Note 2 2 ...
Page 27
... ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52D64322A ACTION Idle after tRP Idle after tRP Idle after tRP Row Active after tRCD Row Active after tRCD Idle after tRFC Idle after tRFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: Jan ...
Page 28
... X X Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52D64322A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: Jan ...
Page 29
... ESMT Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1 Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 29/46 ...
Page 30
... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52D64322A Publication Date: Jan. 2009 Revision: 1.4 30/46 ...
Page 31
... Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.. Elite Semiconductor Memory Technology Inc M52D64322A ...
Page 32
... Precharge Row Active ( A - Bank ) ( A - Bank ) SHZ M52D64322A ...
Page 33
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. before row precharge , will be written. RDL Publication Date: Jan. 2009 Revision: 1.4 M52D64322A 33/46 ...
Page 34
... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 ...
Page 35
... To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data interrupt burst write by Row precharge , both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 ...
Page 36
... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note : 1. t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 36/46 ...
Page 37
... ESMT Read & Write cycle with Auto Precharge @ Burst Length = 4 *Note : 1. t should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc. before internal precharge start. RAS M52D64322A Publication Date: Jan. 2009 Revision: 1.4 37/46 ...
Page 38
... ESMT Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 *Note : 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 38/46 ...
Page 39
... Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 39/46 ...
Page 40
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. M52D64322A Publication Date: Jan. 2009 Revision: 1.4 40/46 ...
Page 41
... Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t 3. Can not violate minimum refresh specification. (64ms) Elite Semiconductor Memory Technology Inc. prior to Row active command. SS M52D64322A Publication Date: Jan. 2009 Revision: 1.4 41/46 ...
Page 42
... CKE going high to complete self refresh exit. RFC 7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit. Elite Semiconductor Memory Technology Inc. is required before exit from self refresh. RAS Publication Date: Jan. 2009 Revision: 1.4 M52D64322A 42/46 ...
Page 43
... CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Extended Mode Register Set Cycle Publication Date: Jan. 2009 Revision: 1.4 M52D64322A 43/46 ...
Page 44
... Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.30 0.35 0.40 0.012 0.586 0.40 0.45 0.50 0.016 7.90 8.00 8.10 0.311 12.90 13.00 13.10 0.508 6.40 11.20 0.80 M52D64322A Norm Max 0.039 0.014 0.016 0.023 0.018 0.020 0.315 0.319 0.512 0.516 0.252 0.441 0.031 Publication Date: Jan. 2009 Revision: 1.4 44/46 ...
Page 45
... Modify DC/AC characteristics 1. Modify ICC spec 2008.03.11 2. Modify RC(min) t (max) SHZ 1.Move revision history to the last 2.Modify the specification of Icc6 2009.01.08 3.Modify the description about self refresh operation M52D64322A Description , and RFC(min) SAC(max) SS(min) SH(min) Publication Date: Jan. 2009 Revision: 1.4 45/46 ...
Page 46
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M52D64322A Publication Date: Jan. 2009 Revision: 1.4 46/46 ...