m52s128168a-7tig Elite Semiconductor Memory Technology Inc., m52s128168a-7tig Datasheet

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... Extended Mode Register CS RAS CAS WE Elite Semiconductor Memory Technology Inc. Preliminary All inputs except data & DM are sampled at the rising edge of the system clock(CLK) Data I/O transitions on both edges of data strobe (DQS) DQS is edge-aligned with data for READ; center-aligned with data for WRITE ...

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... RAS Column address strobe CAS Write enable WE V Ground SS V Power DD Bi-directional Data Strobe. LDQS corresponds to the data on DQ0~DQ7; LDQS, UDQS UDQS correspond to the data on DQ8~DQ15. Elite Semiconductor Memory Technology Inc. Preliminary DQ0 V DDQ DD V DQ1 DQ2 SSQ V DQ3 ...

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... Input Voltage Level, CLK and CLK inputs Input Differential Voltage, CLK and CLK inputs Input leakage current Output leakage current Notes the magnitude of the difference between the input level on CLK and the input level on CLK . ID . Elite Semiconductor Memory Technology Inc. Preliminary Symbol OUT V DD ...

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... Bank Active) I CC3NS I CC4R Operating Current (Burst Mode) I CC4W Refresh Current I CC5 Elite Semiconductor Memory Technology Inc. Preliminary ° Test Condition (min (min), CKE = High /CS = High between valid commands, address inputs are switching, data input signals are stable ...

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... DD DDQ A Parameter Input capacitance (A0~A11, BA0~BA1, CKE RAS , CAS , WE ) Input capacitance (CLK, CLK ) Data & DQS input/output capacitance Input capacitance (DM) Elite Semiconductor Memory Technology Inc. Preliminary CKE = Low High, TCSR range (min), address & Banks control & data inputs are ...

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... DQS falling edge to CLK rising-setup time DQS falling edge from CLK rising-hold time Data strobe edge to output data edge Data-out high-impedance window from CLK/ CLK Data-out low-impedance window from CLK/ CLK Elite Semiconductor Memory Technology Inc. Preliminary ° = 1.7V~ 1.9V 1MHz) ° ...

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... Load Mode Register / Extended Mode register t MRD cycle time Exit self refresh to first valid t XSR command Exit power-down mode first valid command Autoprecharge write t DAL recovery+Precharge time Elite Semiconductor Memory Technology Inc. Preliminary -7.5 min max t min or t min - min QHS - ...

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... New row active of the associated bank can be issued Burst stop command is valid at every burst length sampling at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). Elite Semiconductor Memory Technology Inc. Preliminary CKEn-1 CKEn CS ...

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... Elite Semiconductor Memory Technology Inc. Preliminary DDQ ...

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... Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 0 0 BA1 BA0 Operating Mode 0 0 MRS Cycle 1 0 EMRS Cycle * RFU should stay “0” during MRS cycle Elite Semiconductor Memory Technology Inc. Preliminary A11 RFU* CAS Latency CAS Latency Latency 0 0 ...

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... ESMT Burst Length Address (A2, A1,A0 Elite Semiconductor Memory Technology Inc. Preliminary Burst Address Ordering for Burst Length Starting Sequential Mode xx0 0, 1 xx1 1, 0 x00 x01 x10 x11 000 ...

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... If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored has +/-5°C tolerance BA1 BA0 A11 A10 RFU should stay “0” during EMRS cycle Elite Semiconductor Memory Technology Inc. Preliminary RFU* PASR Internal TCSR DS M53D128168A ...

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... The Mobile DDR SDRAM is put in NOP mode when CS is actived and by deactivating RAS , CAS and WE . For both Deselect and NOP, the device should finish the current operation when this command is issued. Elite Semiconductor Memory Technology Inc. Preliminary (min.) must be satisfied until the precharge command can be issued. ...

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... This command is used after the row activate command to initiate the burst write of data. The write command is initiated by activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of the burst will be determined by the values programmed during the MRS command. Elite Semiconductor Memory Technology Inc. Preliminary 2 ...

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... Elite Semiconductor Memory Technology Inc. Preliminary ...

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... DQ bus prior to valid input write data. Once the Burst Terminate command has been issued, the minimum delay to a Write command = RU(CL) [CL is the CAS Latency and RU means round up to the nearest integer illegal for a Write command to interrupt a Read with autoprecharge command. Elite Semiconductor Memory Technology Inc. Preliminary Latency = 3> ...

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... In all cases, a Precharge operation cannot be initiated unless t satisfied. This includes Read with autoprecharge commands where t autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Preliminary 2 3 ...

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... Length = 4> Elite Semiconductor Memory Technology Inc. Preliminary ...

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... Mobile DDR SDRAM drives them during a read operation input Write data is masked by the Read command, the DQS inputs are ignored by the Mobile DDR SDRAM illegal for a Read command interrupt a Write with autoprecharge command. Elite Semiconductor Memory Technology Inc. Preliminary 2 ...

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... This includes Write with autoprecharge commands where t autoprecharge command has the same timing as a Write command followed by the earliest possible Precharge command which does not interrupt the burst. Elite Semiconductor Memory Technology Inc. Preliminary ) is required from the last data to precharge command. When precharge command is ...

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... L 7. When the burst terminates, the DQ and DQS pins are tristated. The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s). Elite Semiconductor Memory Technology Inc. Preliminary 1 ...

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... Note : At burst read / write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Preliminary (min) is satisfied ...

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... AUTO REFRESH command and the next AUTO REFRESH command is 8x15.6 μ Elite Semiconductor Memory Technology Inc. Preliminary rite ...

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... REF Precharge Elite Semiconductor Memory Technology Inc. Preliminary for locking of DLL. XSRD PDEX t IS ...

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... READ Elite Semiconductor Memory Technology Inc. Preliminary Address DESEL H X NOP L BA Burst Stop X BA, CA, A10 READ / WRITE H BA, RA Active L BA, A10 PRE / PREA H X Refresh L Op-Code Mode-Add ...

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... WRITE with AUTO PRECHARGE Elite Semiconductor Memory Technology Inc. Preliminary Address DESEL H X NOP L BA Burst Stop H BA, CA, A10 READ/READA L BA, CA, A10 WRITE/WRITEA H BA, RA Active L BA, A10 PRE / PREA H ...

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... WRITE RECOVERING Elite Semiconductor Memory Technology Inc. Preliminary Address DESEL H X NOP L BA Burst Stop X BA, CA, A10 READ/WRITE H BA, RA Active L BA, A10 PRE / PREA H X Refresh L Op-Code Mode-Add ...

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... Same bank’s previous auto precharg will not be performed. But if the bank is different, previous auto precharge will be performed. 7. Refer to “Read with Auto Precharge: for more detailed information. ILLEGAL = Device operation and / or data integrity are not guaranteed. Elite Semiconductor Memory Technology Inc. Preliminary Address WE ...

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... EXIT. 2. Power-Down and Self-Refresh can be entered only from All Bank Idle state. 3. The Deep Power Down mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down mode. Elite Semiconductor Memory Technology Inc. Preliminary Add CS ...

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... READ Active Note lesser clock transition collectively when a bank is active Elite Semiconductor Memory Technology Inc. Preliminary BAa t ...

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... ACTIVE ACTIVE Elite Semiconductor Memory Technology Inc. Preliminary BAa BAb BAb ...

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... BAa ACTIVE Elite Semiconductor Memory Technology Inc. Preliminary BAa BAb ACTIVE ...

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... Note 1. The row active command of the precharge bank can be issued after t The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same bank is illegal. Elite Semiconductor Memory Technology Inc. Preliminary ...

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... Note 1. The row active command of the precharge bank can be issued after t The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. Elite Semiconductor Memory Technology Inc. Preliminary ...

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... BAa READ Elite Semiconductor Memory Technology Inc. Preliminary BAa PRE CHARGE M53D128168A ...

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... READ READ Elite Semiconductor Memory Technology Inc. Preliminary M53D128168A ...

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... BAa READ Elite Semiconductor Memory Technology Inc. Preliminary Burst Stop M53D128168A BAb ...

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... BAa WRITE Elite Semiconductor Memory Technology Inc. Preliminary M53D128168A ...

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... BAa WRITE Elite Semiconductor Memory Technology Inc. Preliminary ...

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... WRITE Elite Semiconductor Memory Technology Inc. Preliminary BAb ...

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... WRITE Elite Semiconductor Memory Technology Inc. Preliminary ...

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... In case of 2/CS, 2CKE device with 2/CS & 2CKE, 200μs wait tine is required even if only 1 device exits from Deep Power Down. 6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands and a load mode register sequence. Elite Semiconductor Memory Technology Inc. Preliminary M53D128168A Publication Date : Sep. 2008 Revision : 1.4 ...

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... Elite Semiconductor Memory Technology Inc. Preliminary HIGH ...

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... ESMT PACKING DIMENSIONS 60-BALL DDR SDRAM ( 8x10 mm ) Symbol Φ Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Preliminary Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.25 0.30 0.35 0.010 0.66 0.35 0.40 0.45 0.014 7.95 8.00 8.05 0.313 9.95 10.00 10.05 0.392 6.40 BSC 7.20 BSC 0.80 BSC M53D128168A Norm Max 0 ...

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... ESMT PACKING DIMENSIONS 60-BALL DDR SDRAM ( 8x13 mm ) Symbol Φ Controlling dimension : Millimeter. Elite Semiconductor Memory Technology Inc. Preliminary Dimension in mm Dimension in inch Min Norm Max Min 1.20 0.30 0.35 0.40 0.012 0.80 0.40 0.45 0.50 0.016 7.90 8.00 8.10 0.311 12.90 13.00 13.10 0.508 6.40 11.0 0.80 1.00 M53D128168A Norm Max 0.047 ...

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... ESMT Revision History Revision 1.0 1.1 1.2 1.3 1.4 Elite Semiconductor Memory Technology Inc. Preliminary Date 2007.11.16 Original 1. Change BGA package 2008.01.02 2. Modify tIS 2008.01.16 Add 8x10mm BGA package 1. Move Revision History to the last 2008.06.13 2. Modify tIS Modify the arrangement of 60 Ball BGA (ball 2008.09.01 ...

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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Preliminary Important Notice M53D128168A Publication Date : Sep ...