hn58x2464stie Renesas Electronics Corporation., hn58x2464stie Datasheet
hn58x2464stie
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hn58x2464stie Summary of contents
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HN58X2432SI/HN58X2464SI Two-wire serial interface 32k EEPROM (4-kword × 8-bit)/64k EEPROM (8-kword × 8-bit) Description HN58X2432SI, HN58X2464SI are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by ...
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... Internal organization Operating voltage Frequency Package 32k bit (4096 × 8-bit) HN58X2432SFPIE 64k bit (8192 × 8-bit) HN58X2464SFPIE 32k bit (4096 × 8-bit) HN58X2432STIE 64k bit (8192 × 8-bit) HN58X2464STIE Pin Arrangement V Rev.2.00, Jan.11.2005, page 1 5.5 V 400 kHz 1 5.5 V 400 kHz ...
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HN58X2432SI/HN58X2464SI Pin Description Pin name SCL SDA Block Diagram Control logic A0, A1, A2 SCL SDA Absolute Maximum Ratings Parameter Supply voltage relative Input ...
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HN58X2432SI/HN58X2464SI DC Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Operating temperature (min): −1.0 V for pulse width ≤ 50 ns. Note − DC Characteristics ( +85 Parameter Symbol Min Input ...
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HN58X2432SI/HN58X2464SI − AC Characteristics ( +85 Test Conditions • Input pules levels: 0.2 × 0.8 × • Input rise and fall time: ≤ ...
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HN58X2432SI/HN58X2464SI Timing Waveforms Bus Timing t F SCL t SU.STA t HD.STA SDA (in SDA (out) t SU.WP WP Write Cycle Timing SCL D0 in SDA Write data (Address (n)) Rev.2.00, Jan.11.2005, page 1/f SCL ...
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HN58X2432SI/HN58X2464SI Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum ...
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HN58X2432SI/HN58X2464SI Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V code provided from ...
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HN58X2432SI/HN58X2464SI Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the ...
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HN58X2432SI/HN58X2464SI Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open ...
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HN58X2432SI/HN58X2464SI Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code ...
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HN58X2432SI/HN58X2464SI Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 32kbit and 64kbit EEPROMs receive 2 sequence 8-bit ...
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HN58X2432SI/HN58X2464SI Page Write: The EEPROM is capable of the page write operation which allows any number of bytes bytes to be written in a single write cycle. The page write is the same sequence as the byte ...
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HN58X2432SI/HN58X2464SI Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word ...
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HN58X2432SI/HN58X2464SI Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter ...
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HN58X2432SI/HN58X2464SI Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word(R/W=0) and memory address (2 × 8-bit) sequentially. The ...
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HN58X2432SI/HN58X2464SI Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming ...
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HN58X2432SI/HN58X2464SI Notes Data Protection at V On/Off CC When V is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) CC may act as a trigger and turn the EEPROM to unintentional ...
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HN58X2432SI/HN58X2464SI Package Dimensions HN58X2432SFPIE/HN58X2464SFPIE (FP-8DBV) 4.89 5.15 Max 0.69 Max 1.27 *0.40 ± 0.05 *Pd Plating Rev.2.00, Jan.11.2005, page 6.02 ± 0.18 1.06 0 ˚ – 8 ˚ + 0.289 0.60 – 0.194 ...
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... HN58X2432SI/HN58X2464SI HN58X2432STIE/HN58X2464STIE (TTP-8DAV) 3.00 3.30 Max 0.65 *0.20 ± 0.05 0.13 M 0.805 Max 0.10 *Pd Plating Rev.2.00, Jan.11.2005, page 1.00 6.40 ± 0.20 0˚ – 8˚ 0.50 ± 0.10 Package Code TTP-8DAV JEDEC — JEITA — Mass (reference value) 0.034 g Unit: mm ...
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... Initial issue 1.00 Oct. 27, 2003 Change format issued by Renesas Technology Corp. Deletion of Preliminary 2 Ordering Information Addition of HN58X2432SFPIE, HN58X2464SFPIE, HN58X2432STIE, HN58X2464STIE, HN58X2432SNIE, HN58X2464SNIE 19 Package Dimensions FP-8DB to FP-8DB, FP-8DBV TTP-8DA to TTP-8DA, TTP-8DAV TNP-8DA to TNP-8DA, TNP-8DAV 2.00 Jan.11.2005 Deletion of package : SON (TNP-8DA, TNP-8DAV) ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...