hn58x24256as Renesas Electronics Corporation., hn58x24256as Datasheet

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hn58x24256as

Manufacturer Part Number
hn58x24256as
Description
Two-wire Serial Interface 256k Eeprom 32-kword ?? 8-bit
Manufacturer
Renesas Electronics Corporation.
Datasheet
HN58X24256AS
Two-wire serial interface
256k EEPROM (32-kword × 8-bit)
Description
HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 64-byte page programming function to make their write operation faster.
Note: Renesas Technology’s serial EEPROM are authorized for using consumer applications such as
Features
• Single supply: 1.8 V to 5.5 V
• Two-wire serial interface (I
• Clock frequency: 400 kHz
• Power dissipation:
• Automatic page write: 64-byte/page
• Write cycle time: 5 ms
• Endurance: 10
• Data retention: 10 Years
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Renesas Technology’s Sales Dept. regarding specifications.
Rev.0.01, Mar.22.2007, page 1 of 20
 Standby: 3 µA (max)
 Active (Read): 1 mA (max)
 Active (Write): 5 mA (max)
cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology’s
sales office before using industrial applications such as automotive systems, embedded controllers,
and meters.
6
Cycles
2
C serial bus)
REJ03C0316-0001
Mar.22.2007
Preliminary
Rev.0.01

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hn58x24256as Summary of contents

Page 1

... HN58X24256AS Two-wire serial interface 256k EEPROM (32-kword × 8-bit) Description HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 64-byte page programming function to make their write operation faster. Note: Renesas Technology’ ...

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... TSSOP 14-pin: 2,000 IC/reel  SOP 8-pin: 2,500 IC/reel • Temperature range: −40 to +85°C • Lead free products. Ordering Information Type No. Internal organization HN58X24256ASFPI 256k bit (32768 × 8-bit) HN58X24256ASTI 256k bit (32768 × 8-bit) Pin Arrangement 8-pin SOP ...

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... HN58X24256AS Pin Description Pin name SCL SDA Block Diagram Control logic A0, A1, A2 SCL SDA Absolute Maximum Ratings Parameter Supply voltage relative Input voltage relative Operating temperature range* Storage temperature range Notes: 1. Including electrical characteristics and data retention. ...

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... HN58X24256AS DC Operating Conditions Parameter Supply voltage Input high voltage Input low voltage Operating temperature Notes (min): −1.0 V for pulse width ≤ Characteristics (Ta = −40 to +85°C, V Parameter Symbol Min Input leakage current I LI Output leakage current I LO Standby V current ...

Page 5

... HN58X24256AS AC Characteristics (Ta = −40 to +85°C, V Test Conditions • Input pules levels:  0.2 ×  0.8 × • Input rise and fall time: ≤ • Input and output timing reference levels: 0.5 × V • Output load: TTL Gate + 100 pF Parameter Clock frequency ...

Page 6

... HN58X24256AS Timing Waveforms Bus Timing t F SCL t SU.STA t HD.STA SDA (in SDA (out) t SU.WP WP Write Cycle Timing SCL D0 in SDA Write data (Address (n)) Rev.0.01, Mar.22.2007, page 1/f SCL t t LOW HIGH t HD.DAT t SU.DAT t DH Stop condition Start condition t WC ACK ...

Page 7

... HN58X24256AS Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer ...

Page 8

... HN58X24256AS Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to V code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated ...

Page 9

... HN58X24256AS Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation (See start condition and stop condition). Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition ...

Page 10

... HN58X24256AS Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words ...

Page 11

... HN58X24256AS Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses “ ...

Page 12

... HN58X24256AS Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 128kbit and 256kbit EEPROMs receive 2 sequence 8-bit memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment " ...

Page 13

... HN58X24256AS Page Write: The EEPROM is capable of the page write operation which allows any number of bytes bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every ninth bit acknowledgment ...

Page 14

... HN58X24256AS Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during a internally-timed write cycle. Acknowledge polling will operate when the R/W code = “ ...

Page 15

... HN58X24256AS Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = “1”. Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word (R/W is “ ...

Page 16

... HN58X24256AS Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 × 8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment “ ...

Page 17

... HN58X24256AS Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”. The address will roll over and returns address zero if it reaches the last address of the last page ...

Page 18

... HN58X24256AS Notes Data Protection at V On/Off CC When V is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) CC may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. • ...

Page 19

... HN58X24256AS Package Dimensions HN58X24256ASFPI (PRSP0008DF-B / Previous Code: FP-8DBV) JEITA Package Code RENESAS Code Previous Code P-SOP8-3.9x4.89-1.27 PRSP0008DF Index mark Rev.0.01, Mar.22.2007, page MASS[Typ.] FP-8DBV 0.08g Terminal cross section ( Ni/Pd/Au plating ) Detail F NOTE) 1. DIMENSIONS" ...

Page 20

... HN58X24256AS HN58X24256ASTI (PTSP0014JA-C / Previous Code: TTP-14DBV) JEITA Package Code RENESAS Code Previous Code P-TSSOP14-4.4x5-0.65 PTSP0014JA-C TTP-14DBV * Index mark Rev.0.01, Mar.22.2007, page MASS[Typ.] 0.05g Terminal cross section ( Ni/Pd/Au plating ) Detail F NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" ...

Page 21

... Revision History Rev. Date Contents of Modification Page Description 0.01 Mar. 22, 2007 Initial issue  HN58X24256AS Data Sheet ...

Page 22

Sales Strategic Planning Div. Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness ...

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