sm72295x National Semiconductor Corporation, sm72295x Datasheet - Page 9

• Manufacturer Part Number: sm72295x
• Description: Photovoltaic Full Bridge Driver
• Manufacturer: National Semiconductor Corporation

Power Dissipation Considerations
The total IC power dissipation is the sum of the gate driver
losses and the bootstrap diode losses. The gate driver losses
are related to the switching frequency (f), output load capac-
itance on LO and HO (C
be roughly calculated as:
There are some additional losses in the gate drivers due to
the internal CMOS stages used to buffer the LO and HO out-
puts. The following plot shows the measured gate driver
power dissipation versus frequency and load capacitance. At
higher frequencies and load capacitance values, the power
dissipation is dominated by the power losses driving the out-
put loads and agrees well with the above equation. This plot
can be used to approximate the power losses due to the gate
drivers.
The bootstrap diode power loss is the sum of the forward bias
power loss that occurs while charging the bootstrap capacitor
and the reverse bias power loss that occurs during reverse
recovery. Since each of these events happens once per cycle,
the diode power loss is proportional to frequency. Larger ca-
pacitive loads require more current to recharge the bootstrap
capacitor resulting in more losses. Higher input voltages
(V
es. The following plot was generated based on calculations
and lab measurements of the diode recovery time and current
under several operating conditions. This can be useful for ap-
proximating the diode power dissipation. The total IC power
dissipation can be estimated from the previous plots by sum-
ming the gate drive losses with the bootstrap diode losses for
the intended application.
IN
) to the half bridge result in higher reverse recovery loss-
Gate Driver Power Dissipation (LO + HO)
V
CC
= 12V, Neglecting Diode Losses
P
DGATES
L
), and supply voltage (V
= 2 • f • C
L
• V
DD
2
DD
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) and can
9
Layout Considerations
The optimum performance of high and low-side gate drivers
cannot be achieved without taking due considerations during
circuit board layout. Following points are emphasized.
1.
2.
3.
4.
Low ESR / ESL capacitors must be connected close to
the IC, between VDD and VSS pins and between the HB
and HS pins to support the high peak currents being
drawn from VDD during turn-on of the external MOSFET.
To prevent large voltage transients at the drain of the top
MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
In order to avoid large negative transients on the switch
node (HS pin), the parasitic inductances in the source of
top MOSFET and in the drain of the bottom MOSFET
(synchronous rectifier) must be minimized.
Grounding Considerations:
a.
is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical
area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the
MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
b.
capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET
body diode. The bootstrap capacitor is recharged on a
cycle-by-cycle basis through the bootstrap diode from
the ground referenced VDD bypass capacitor. The
recharging occurs in a short time interval and involves
high peak current. Minimizing this loop length and area
on the circuit board is important to ensure reliable
operation.
The first priority in designing grounding connections
The second high current path includes the bootstrap
Diode Power Dissipation V
IN
= 50V
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