HEF4049BP,652 NXP Semiconductors, HEF4049BP,652 Datasheet
HEF4049BP,652
Specifications of HEF4049BP,652
933277650652
HEF4049BPN
Related parts for HEF4049BP,652
HEF4049BP,652 Summary of contents
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HEF4049B Hex inverting buffers Rev. 08 — 2 December 2009 1. General description The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ ...
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... NXP Semiconductors 5. Functional diagram 001aai331 Fig 1. Logic symbol 6. Pinning information 6.1 Pinning Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin 10, 12, 15 HEF4049B_8 Product data sheet A Y mna341 Fig 2. Logic diagram for one gate HEF4049B n. n. 001aae602 Description supply voltage output Rev. 08 — ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin 11 n.c. 13 Functional description Table 3. Guaranteed fan-out Driven element Standard TTL Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD I input clamping current IK V input voltage ...
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... NXP Semiconductors Table 5. Recommended operating conditions Symbol Parameter Δt/ΔV input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics unless otherwise specified Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics ≤ pF ns Symbol Parameter Conditions t HIGH to LOW nA to nY; PHL propagation delay see t LOW to HIGH nA to nY; PLH propagation delay see t HIGH to LOW output see THL transition time t LOW to HIGH output see TLH transition time [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C Table 8 ...
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... NXP Semiconductors 12. Waveforms Measurement points are given in V and V are typical output voltage levels that occur with the output load Fig 5. Input (nA) to output (nY) propagation delays and transition times Table 9. Measurement points Input 0. Test data is given in Table 10. Definitions for test circuit Load capacitance including jig and probe capacitance ...
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... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT b max. min. max. 1.73 mm 4.2 0.51 3.2 1.30 0.068 inches 0.17 0.02 0.13 0.051 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 11. Abbreviations Acronym Description DTL Diode Transistor Logic LOCMOS Local Oxidation CMOS TTL Transistor Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date HEF4049B_8 20091202 • Modifications: Section 8 “Limiting values” HEF4049B_7 20090721 HEF4049B_6 20090325 HEF4049B_5 20081111 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 14 Abbreviations ...