lc5256b-75t128i Lattice Semiconductor Corp., lc5256b-75t128i Datasheet

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lc5256b-75t128i

Manufacturer Part Number
lc5256b-75t128i
Description
2.5v In-system Programmable Superwide High Density Plds Tm
Manufacturer
Lattice Semiconductor Corp.
Datasheet
September 2003
Features
www.latticesemi.com
Table 1. ispMACH 5000B Family Selection Guide
Macrocells
User I/O Options
t
t
t
f
Supply Voltage (V)
Package
PD
S
CO
MAX
– Set-up with 0 Hold (ns)
High Speed Logic Implementation
sysIO
Ease of Design
Broad Device Offering
(ns)
(ns)
• SuperWIDE 68-input logic block
• Up to 35 product terms per output
• Single-level Global Routing Pool (GRP)
• LVCMOS 1.8, 2.5 and 3.3
• LVTTL
• SSTL 2 (I and II)
• SSTL 3 (I and II)
• CTT 3.3, CTT 2.5
• HSTL (I and III)
• PCI 3.3
• GTL+
• AGP-1X
• LVDS (clock input)
• LVPECL (clock input)
• Programmable drive strength
• Product term sharing
• Extensive clocking and OE capability
• 128 to 512 macrocells
• 92 to 256 I/Os
• 128 to 484 pins/balls in TQFP, PQFP and fpBGA
• Commercial and industrial temperature ranges
(MHz)
packages
TM
Capability
128-pin TQFP
ispMACH
5128B
128
275
3.0
1.7
2.2
2.5
92
ispMACH 5000B Family
1
ispMACH 5000B Introduction
The ispMACH 5000B represents the next generation of
Lattice’s SuperWIDE CPLD architecture. Through their
wide 68-input blocks, these devices give significantly
improved speed performance for typical designs over
architectures with a lower number of inputs.
In addition to the unique benefits of the SuperWIDE
architecture, the ispMACH 5000B provides sysIO capa-
bility to provide support for a variety of advanced I/O
standards.
The ispMACH 5000B devices consist of multiple Super-
WIDE 68-input, 32-macrocell Generic Logic Blocks
(GLBs) interconnected by a single-level routing system
referred to as the Global Routing Pool (GRP). Figure 1
shows the ispMACH 5000B block diagram. Together,
the GLBs and the GRP allow designers to create large
designs in a single device without compromising perfor-
mance.
256-ball fpBGA
208-pin PQFP
128-pin TQFP
ispMACH
Easy System Integration
92/144
• 2.5V power supply
• Hot socketing
• Input pull-up, pull-down or Bus-keeper
• Open drain capability
• Macrocell-based power management
• IEEE 1149.1 Boundary Scan testable
• IEEE 1532 compliant In-System Programmable
5256B
256
250
4.0
2.1
2.7
2.5
(Pin-by-pin selectable)
(ISP™)
SuperWIDE High Density PLDs
2.5V In-System Programmable
TM
256-ball fpBGA
208-pin PQFP
ispMACH
156/186
5384B
384
250
4.0
2.1
2.7
2.5
TM
256-ball fpBGA
484-ball fpBGA
208-pin PQFP
156/196/256
ispMACH
5512B
512
200
4.5
2.5
2.8
2.5
Data Sheet
5kb_11.1

Related parts for lc5256b-75t128i

lc5256b-75t128i Summary of contents

Page 1

September 2003 Features High Speed Logic Implementation • SuperWIDE 68-input logic block • product terms per output • Single-level Global Routing Pool (GRP) TM sysIO Capability • LVCMOS 1.8, 2.5 and 3.3 • LVTTL • SSTL 2 ...

Page 2

Lattice Semiconductor Figure 1. Functional Block Diagram I/O Bank 0 Generic VCCO0 VREF0 GCLK0 TOE GCLK1 Generic VCCO1 VREF1 I/O Bank 1 The GLB has 68 inputs coming from the GRP and contains 163 product terms. These product terms form ...

Page 3

Lattice Semiconductor and complement form for every product term. The three control product terms are used for shared reset, clock and output enable functions. AND-Array The programmable AND-array consists of 68 inputs and 163 output product terms. The 68 inputs ...

Page 4

Lattice Semiconductor Figure 3. ispMACH 5000B Dual-OR Array From PT0 From PT1 From PT2 From PT3 From PT4 Product Term Sharing Array The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array and 32 outputs directly ...

Page 5

Lattice Semiconductor Macrocell The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks and control ...

Page 6

Lattice Semiconductor each of these signals. The output of the OE MUX goes through a logical AND with the TOE signal to allow easy tri- stating of the outputs for testing purposes. The four Shared PTOE signals are derived from ...

Page 7

Lattice Semiconductor For more information on the sysIO capability, please refer to technical note number TN1000, sysIO Design and Usage Guidelines available on the Lattice web site at www.latticesemi.com. Table 2. ispMACH 5000B Supported I/O Standards LVTTL LVCMOS 3.3 LVCMOS ...

Page 8

Lattice Semiconductor Figure 7. ispMACH 5000B Global Clock MUX GCLK0 VREF0 GCLK1 VREF1 VREF2 GCLK2 VREF3 GCLK3 Power Management The ispMACH 5000B devices provide unique power management controls. The device has two power settings, high power and low power, on ...

Page 9

Lattice Semiconductor that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532 as the communication interface through which ISP is achieved, customers get the benefi standard, well-defined interface. The ispMACH 5000B devices ...

Page 10

Lattice Semiconductor Absolute Maximum Ratings Supply Voltage -0.5 to 4.05V CC Output Supply Voltage ...

Page 11

Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input I/O Input I/O Weak Pull-up Resistor Current I/O Weak Pull-down Resistor Current Bus ...

Page 12

Lattice Semiconductor sysIO Recommended Operating Conditions Standard LVTTL LVCMOS 3.3 1 LVCMOS 2.5 LVCMOS 1.8 PCI 3.3 AGP-1X SSTL 3, Class I, II SSTL 2, Class I, II CTT 3.3 CTT 2.5 HSTL GTL+ 1. Software default setting. V (V) ...

Page 13

Lattice Semiconductor sysIO DC Electrical Characteristics V IL Input/Output Standard Min (V) Max (V) LVCMOS 3.3 -0.3 LVTTL -0.3 1 LVCMOS 2.5 -0.3 LVCMOS 2.5 -0.3 LVCMOS 1.8 -0.3 PCI 3.3 -0.3 AGP-1X -0.3 SSTL3 class I -0.3 V REF ...

Page 14

Lattice Semiconductor ispMACH 5128B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...

Page 15

Lattice Semiconductor ispMACH 5256B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...

Page 16

Lattice Semiconductor ispMACH 5384B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...

Page 17

Lattice Semiconductor ispMACH 5512B External Switching Characteristics Parameter Description t Data propagation delay, 5-PT bypass PD t Propagation delay PD_PTSA t GLB register setup time before clock, 5-PT S bypass t GLB register setup time before clock S_PTSA t GLB ...

Page 18

Lattice Semiconductor Timing Model The task of determining the timing through the ispLSI 5000B family, just as any CPLD, is relatively simple. The tim- ing model provided in Figure 8 shows the specific delay paths. Once the implementation of a ...

Page 19

Lattice Semiconductor ispMACH 5128B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...

Page 20

Lattice Semiconductor ispMACH 5256B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...

Page 21

Lattice Semiconductor ispMACH 5384B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...

Page 22

Lattice Semiconductor ispMACH 5512B Internal Timing Parameters Parameter Description In/Out Delays t Input Buffer Delay IN t Global Clock Input Buffer Delay GCLK_IN t Global OE Pin Delay GOE t Delay through Output Buffer BUF t Output Enable Time EN ...

Page 23

Lattice Semiconductor ispMACH 5128B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI GCLK_IN LVCMOS18_in t t RST, GOE GCLK_IN LVCMOS25_in t t RST, GOE t , ...

Page 24

Lattice Semiconductor ispMACH 5128B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4A_out EN, DIS, BUF LVCMOS33_5mA_out ...

Page 25

Lattice Semiconductor ispMACH 5128B Timing Adders (Cont). Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE Note: Open drain timing is the same as corresponding LVCMOS timing. -4 Base Parameter Min. Max. ...

Page 26

Lattice Semiconductor ispMACH 5256B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI GCLK_IN LVCMOS18_in t t RST, GOE GCLK_IN LVCMOS25_in t t RST, GOE t , ...

Page 27

Lattice Semiconductor ispMACH 5256B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4A_out EN, DIS, BUF LVCMOS33_5mA_out ...

Page 28

Lattice Semiconductor ispMACH 5256B Timing Adders (Cont). Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE 4 t ROUTE 5 t ROUTE 6 t ROUTE 7 t ROUTE Note: Open drain timing ...

Page 29

Lattice Semiconductor ispMACH 5384B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI LVCMOS18_in t t IN, GCLK_IN RST, GOE LVCMOS25_in t t IN, GCLK_IN RST, GOE LVCMOS33_in t t IN, ...

Page 30

Lattice Semiconductor ispMACH 5384B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4mA_out EN, DIS, BUF LVCMOS33_5mA_out ...

Page 31

Lattice Semiconductor ispMACH 5384B Timing Adders (Cont.) Adder Type t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE 4 t ROUTE 5 t ROUTE 6 t ROUTE 7 t ROUTE 8 t ROUTE 9 ...

Page 32

Lattice Semiconductor ispMACH 5512B Timing Adders Adder Base Type Parameter ROUTE t Input Adders IOI t t IN, GCLK_IN, LVCMOS18_in t t RST, GOE t t IN, GCLK_IN, LVCMOS25_in t t RST, GOE t t IN, GCLK_IN, ...

Page 33

Lattice Semiconductor ispMACH 5512B Timing Adders (Cont.) Adder Base Type Parameter LVCMOS25_8mA_out EN, DIS, BUF LVCMOS25_12mA_out EN, DIS, BUF LVCMOS25_16mA_out EN, DIS, BUF LVCMOS33_4mA_out EN, DIS, BUF LVCMOS33_5mA_out ...

Page 34

Lattice Semiconductor ispMACH 5512B Timing Adders (Cont.) Adder Type t Input Adders IOI CLK0 t GCLK_IN CLK1 t GCLK_IN CLK2 t GCLK_IN CLK3 t GCLK_IN t Additional Block Loading Adders BLA 1 t ROUTE 2 t ROUTE 3 t ROUTE ...

Page 35

Lattice Semiconductor Power Consumption ispMACH 5000B Typical I 600 500 400 300 200 100 0 0 Note: The devices are configured with maximum number of 16-bit counters, typical current at 2.5V, 25°C. Power Estimation Coefficients Device K0 ispMACH 5128B 0.0055 ...

Page 36

Lattice Semiconductor Switching Test Conditions Figure 9 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, volt- age, and other test conditions are shown in Table 3. Figure 9. Output Test Load, ...

Page 37

Lattice Semiconductor Signal Descriptions Signal Names TMS Input - This pin is the Test Mode Select input, which is used to control the IEEE 1149.1 state machine. TCK Input - This pin is the Test Clock input pin, used to ...

Page 38

Lattice Semiconductor ispMACH 5000B Power Supply and NC Connections 1,2 Signal 128-Pin TQFP 208-Pin PQFP VCC 13, 45, 77, 109 11, 48, 74, 115, 152, 178 VCCO0 5, 120 5256B: 18, 189, 203 5384B/5512B: 7, 18, 189, 203 VCCO1 28, ...

Page 39

Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP Pin Number ...

Page 40

Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number ...

Page 41

Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 100 101 102 103 104 105 106 107 108 109 110 111 ...

Page 42

Lattice Semiconductor ispMACH 5128B, 5256B Logic Signal Connections: 128 TQFP (Cont.) Pin Number 127 128 ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP Pin Bank Number Number ...

Page 43

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number ...

Page 44

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number ...

Page 45

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 ...

Page 46

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 ...

Page 47

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 208 PQFP (Cont.) Pin Bank Number Number 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 ispMACH 5256B, 5384B, 5512B ...

Page 48

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - - ...

Page 49

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - ...

Page 50

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number T10 T11 T12 R10 P9 R11 T13 ...

Page 51

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - - L10 L11 K11 R15 P15 R16 P16 N14 N13 - - - - N15 N16 M16 M12 M13 M15 L16 ...

Page 52

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number H14 H13 H16 J10 J12 G16 G15 H12 G12 G13 - - - - F16 F15 F13 F14 F12 E16 G11 F11 F10 B11 ...

Page 53

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - C16 C15 D14 A14 C13 B13 - - A13 A12 A11 - - A10 C11 A9 D12 D11 B10 B9 E11 A8 D10 ...

Page 54

Lattice Semiconductor ispMACH 5256B, 5384B, 5512B Logic Signal Connections: 256 fpBGA (Cont.) Ball Number Bank Number - - - ispMACH 5512B Logic Signal Connections: 484 fpBGA ...

Page 55

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - ...

Page 56

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - - - - AA3 ...

Page 57

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - AB3 Y6 AB4 Y7 AB5 V8 AA7 Y8 AB6 W8 AA8 Y10 - - U8 AB7 U9 AA9 W9 AB8 U10 AB9 V11 AA10 V10 AB10 - ...

Page 58

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number W12 Y11 Y12 AB12 U12 AA12 - - - - Y13 AB13 W13 AA13 U13 AB14 V13 AA14 U14 AB15 Y15 AB16 - - AA15 W14 AB17 Y16 ...

Page 59

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number AA19 V16 AB21 Y18 W18 AA20 W19 Y19 V19 - - - - Y21 W20 AA22 W21 Y22 V20 V21 W22 V18 U20 V22 U19 - - U17 ...

Page 60

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number P17 P19 R21 T22 P21 N20 R22 N21 - - - - M18 N19 P22 M20 N22 N17 M19 M21 L19 L20 - - - - M17 M22 ...

Page 61

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number J19 J22 J21 - - F22 E22 E19 E20 D22 D21 - - - - D20 C22 C18 C19 D17 C21 - - - - - - B16 ...

Page 62

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number A15 D12 A14 B13 - - - - A13 B12 C13 A12 C12 A11 - - - - - - D11 B11 E12 C11 F12 B10 - - ...

Page 63

Lattice Semiconductor ispMACH 5512B Logic Signal Connections: 484 fpBGA (Cont.) Ball Number - - - ispMACH 5000B Family Data Sheet Bank Number - ...

Page 64

... Ordering Information Device Part Number LC5128B-3T128C LC5128B LC5128B-5T128C LC5128B-75T128C LC5256B-4T128C LC5256B-4Q208C LC5256B-4F256C LC5256B-5T128C LC5256B LC5256B-5Q208C LC5256B-5F256C LC5256B-75T128C LC5256B-75Q208C LC5256B-75F256C LC5384B-4Q208C LC5384B-4F256C LC5384B-5Q208C LC5384B LC5384B-5F256C LC5384B-75Q208C LC5384B-75F256C ispMACH 5000B Family Data Sheet LC XXXXB – XXX X Commercial Macrocells Voltage ...

Page 65

... Note: The speed grade for these devices are dual marked. For example, the commercial grade -4xxxxC is also marked with the industrial grade -5xxxxI. The commercial grade is always one speed grade faster than the associated dual mark industrial grade. Device Part Number LC5128B-5T128I LC5128B LC5128B-75T128I LC5128B-10T128I LC5256B-5T128I LC5256B-5Q208I LC5256B-5F256I LC5256B-75T128I LC5256B LC5256B-75Q208I LC5256B-75F256I LC5256B-10T128I LC5256B-10Q208I LC5256B-10F256I LC5384B-5Q208I LC5384B-5F256I LC5384B-75Q208I LC5384B ...

Page 66

Lattice Semiconductor For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispMACH 5000B family: • sysIO Design and Usage Guidelines (TN1000) • Power Estimation in ispMACH 5000B Devices (TN1023) ...

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