atr2434 ATMEL Corporation, atr2434 Datasheet - Page 17

• Manufacturer Part Number: atr2434
• Description: Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
• Manufacturer: ATMEL Corporation

Table 12. Receive SERDES Data A
Table 13. Receive SERDES Valid A
Table 14. Receive SERDES Data B
4822C–ISM–09/04
1
0
Bit
7:0
Bit
7:0
Bit
7:0
EOF A
Full A
7
7
7
Name
Data
Name
Valid
Name
Data
Addr: 0x0A
Addr: 0x0B
Addr: 0x09
Description
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that
the corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES
Data A register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg
0x0A). The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4,
followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Description
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit
3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Description
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by
bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
The End of Frame A bit is used to signal whether an EOF event has occurred on the Channel A receive.
1 = EOF interrupt pending for Channel A
0 = No EOF interrupt pending for Channel A
An EOF condition occurs for the Channel A Receiver when receive has begun and then the number of bit times
specified in the SERDES Control register (0x06) elapse without any valid bits being received. This bit is cleared
by reading the Receive Interrupt Status register (Reg 0x08).
The Full A bit is used to signal when the Receive SERDES Data A register (Reg 0x09) is filled with data.
1 = Receive SERDES Data A full interrupt pending
0 = No Receive SERDES Data A full interrupt pending
A Full A condition occurs when data is transferred from the Channel A Receiver into the Receive SERDES Data
A Register (Reg 0x09). This could occur when a complete byte is received or when an EOF event occurs
whether or not a complete byte has been received.
6
6
6
5
5
5
REG_RX_VALID_A
REG_RX_DATA_A
REG_RX_DATA_B
4
4
4
Valid
Data
Data
3
3
3
ATR2434 [Preliminary]
2
2
2
1
1
1
Default: 0x00
Default: 0x00
Default: 0x00
0
0
0
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