atr2434 ATMEL Corporation, atr2434 Datasheet - Page 23

• Manufacturer Part Number: atr2434
• Description: Wirelessusb 2.4-ghz Dsss Radio Soc - Atmel Corporation
• Manufacturer: ATMEL Corporation

Table 25. Analog Control
Table 26. Channel
4822C–ISM–09/04
Bit
7
6
5
4:3
2
1
0
Bit
7
6:0
Reserved
A+N
Name
Reserved
AGC RSSI
Control
MID Read
Enable
Reserved
PA Output
Enable
PA Invert
Reset
7
7
Name
A+N
Channel
Addr: 0x20
Addr: 0x21
AGC Disable
6
6
Description
The A+N bit is used to specify whether the Synthesizer frequency is generated through the use of the
Channel register (Reg 0x21) or through the use of the Synthesizer A Counter register (Reg 0x01) and the
Synthesizer N Counter register (Reg 0x02).
1 = Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) registers
0 = Channel register (Reg 0x21) is used to generate Synthesizer frequency
When set to 1 the channel value is ignored and the values written in the Synthesizer A Counter register (Reg
0x01) and the Synthesizer N Counter register (Reg 0x02) are used. When set to 0 the values written to the
Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register (Reg 0x02) are ignored
and the channel value is used by the synthesizer. It is recommended that the Channel register (Reg 0x21) is
used as opposed to the Synthesizer A Counter register (Reg 0x01) and the Synthesizer N Counter register
(Reg 0x02) method.
The Channel register (Reg 0x21) is used to determine the Synthesizer frequency when the A+N bit is set to
0. Use of other channels may be restricted by certain regulatory agencies. A value of 1 corresponds to a
communication frequency of 2.402 GHz, while a value of 79 corresponds to a frequency of 2.479 GHz. The
channels are separated from each other by 1 MHz intervals.
Description
This bit is reserved and should be written with zero.
Enables AGC/RSSI control via Reg 0x2E and Reg 0x2F.
The MID Read Enable bit must be set to read the contents of the Manufacturing ID register
(Reg 0x3C-0x3F). Enabling the Manufacturing ID register (Reg 0x3C-0x3F) consumes power. This bit should
only be set when reading the contents of the Manufacturing ID register (Reg 0x3C-0x3F).
These bits are reserved and should be written with zeros.
The Power Amplifier Output Enable bit is used to enable the PACTL pin for control of an external power
amplifier.
1 = PA Control Output Enabled on PACTL pin
0 = PA Control Output Disabled on PACTL pin
The Power Amplifier Invert bit is used to specify the polarity of the PACTL signal when the PaOe bit is set
high. PA Output Enable and PA Invert cannot be simultaneously changed.
1 = PACTL active low
0 = PACTL active high
The Reset bit is used to generate a self clearing device reset.
1 = Device Reset. All registers are restored to their default values
0 = No Device Reset
used to generate Synthesizer frequency
MID Read
Enable
5
5
Reserved
REG_ANALOG_CTL
4
4
REG_CHANNEL
Reserved
Channel
3
3
ATR2434 [Preliminary]
PA Output
Enable
2
2
PaInv
1
1
Default: 0x00
Default: 0x00
Rst
0
0
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