ispgal22v10av Lattice Semiconductor Corp., ispgal22v10av Datasheet

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ispgal22v10av

Manufacturer Part Number
ispgal22v10av
Description
In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic ?
Manufacturer
Lattice Semiconductor Corp.
Datasheet

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© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
www.latticesemi.com
January 2004
Features
High Performance
Low Power
Space-Saving Packaging
Easy System Integration
In-System Programmable
E
Applications Include
Boundary Scan USERCODE Register
• t
• f
• t
• t
• 1.8V core E
• Typical standby power <300µW
• CMOS design techniques provide low static and
• Available in 32-pin QFN (Quad Flat-pack No
• Operation with 3.3V (ispGAL22V10AV), 2.5V
• Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O
• 5V tolerant I/O for LVCMOS 3.3 interface
• Hot-socketing
• Open-drain capability
• Input pull-up, pull-down or bus-keeper
• Lead-free package option
• Programmable output slew rate
• 3.3V PCI compatible
• IEEE 1149.1 boundary scan testable
• 3.3V/2.5V/1.8V in-system programmable
• In-system programmable logic
• 100% tested/100% yields
• High speed electrical erasure (<50ms)
• DMA control
• State machine control
• High speed graphics processing
• Software-driven hardware configuration
• Supports electronic signature
2
output
(ispGAL22V10AC)
dynamic power
lead), 5mm x 5mm body size
(ispGAL22V10AB) or 1.8V (ispGAL22V10AC)
supplies
(ISP™) using IEEE 1532 compliant interface
CELL TECHNOLOGY
PD
MAX
CO
SU
= 1.3 ns clock set-up time
= 2.3ns propagation delay
= 2ns maximum from clock input to data
= 455 MHz maximum operating frequency
2
CMOS
®
technology
1
Introduction
The ispGAL22V10A is manufactured using Lattice
Semiconductor’s advanced E
combines CMOS with Electrically Erasable (E
gate technology. With an advanced E
and full CMOS logic approach, the ispGAL22V10A fam-
ily offers fast pin-to-pin speeds, while simultaneously
delivering low standby power without requiring any
“turbo bits” or other traditional power management
schemes. The ispGAL22V10A can interface with both
3.3V, 2.5V and 1.8V signal levels.
The ispGAL22V10A is functionally compatible with the
ispGAL22LV10, GAL22LV10 and GAL22V10.
Figure 1. Functional Block Diagram
ispGAL22V10AV/B/C
TDO
TMS
TCK
TDI
I/CLK
PROGRAMMING
In-System Programmable Low Voltage
I
I
I
I
I
I
I
I
I
I
I
LOGIC
E
2
CMOS PLD Generic Array Logic
´®
2
CMOS process, which
PRESET
RESET
10
12
14
16
16
12
10
14
8
8
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
2
low-power cell
isp22v10a_02
Data Sheet
2
) floating
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

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ispgal22v10av Summary of contents

Page 1

... CMOS design techniques provide low static and dynamic power Space-Saving Packaging • Available in 32-pin QFN (Quad Flat-pack No lead), 5mm x 5mm body size Easy System Integration • Operation with 3.3V (ispGAL22V10AV), 2.5V (ispGAL22V10AB) or 1.8V (ispGAL22V10AC) supplies • Operation with 3.3V, 2.5V or 1.8V LVCMOS I/O • 5V tolerant I/O for LVCMOS 3.3 interface • Hot-socketing • ...

Page 2

... OLMC, and can therefore be defined by a logic equation. The D flip-flop’s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array MUX CLK MUX 2 ispGAL22V10AV/B/C Data Sheet ...

Page 3

... AND array. Figure 3. Registered Mode AR D CLK SP ACTIVE LOW Figure 4. Combinatorial Mode ACTIVE LOW ispGAL22V10AV/B/C Data Sheet CLK Q SP ACTIVE HIGH ACTIVE HIGH ...

Page 4

... JEDEC Fuse #131 S1 Arch Control Bits SR = Slew Rate Bit OD = Open Drain Bit 4 ispGAL22V10AV/B/C Data Sheet JEDEC Fuse #5676 40 ASYNCHRONOUS RESET (TO ALL REGISTERS) 8 OLMC S1 5808, 5809 SR = 5830 OD = 5831 10 OLMC S1 5810, 5811 SR = 5832 OD = 5833 ...

Page 5

... The software can use these vectors to drive a scan chain 2 low power cell and no sense-amplifiers (full CMOS logic approach), the and V must be the same. The option to set the V CCO CC 5 ispGAL22V10AV/B/C Data Sheet . Outputs can also be configured for CCO CCO CCO inde- ...

Page 6

... Figure 6. Timing Diagram for Power-up INTERNAL REGISTER Q - OUTPUT ACTIVE LOW OUTPUT REGISTER ACTIVE HIGH OUTPUT REGISTER Vcc (min ispGAL22V10AV/B/C Data Sheet Internal Register Reset to Logic "0" Device Pin Reset to Logic "1" Device Pin Reset to Logic "0" ...

Page 7

... T = 105° However, assumes monotonic rise/fall rates for V CCO (MAX (V) CCO Min Max 3.0 3.6 3.0 3.6 2.3 2.7 1.65 1.95 3.0 3.6 7 ispGAL22V10AV/B/C Data Sheet ispGAL ispGAL 22V10AB (2.5V) 22V10AV (3.3V) -0.5 to 5.5V -0.5 to 5.5V -0.5 to 4.5V -0.5 to 4.5V -0.5 to 5.5V -0.5 to 5.5V -65 to 150° C -65 to 150° C -55 to 150°C -55 to 150°C Min Max 1.65 1.95 2.3 2.7 3.0 3 ...

Page 8

... IO IH condition of 3.0V ≤ V ≤ 3.6V. CCO CCO Over Recommended Operating Conditions Condition ispGAL22V10AV/B/C Data Sheet Min Typ Max — — 10 — — 20 — — -80 20 — 150 20 — 150 20 — — 20 — — — — 150 — ...

Page 9

... Output Voltage ( Over Recommended Operating Conditions V IH Max (V) Min (V) 0.80 2.0 0.80 2.0 0.70 1.70 0.63 1.17 0. 1.08 1.5 / 1.8) 0 3.3V V CCO 1.5 2.0 2.5 3.0 3.5 1.8V V CCO 1.0 1.5 2.0 9 ispGAL22V10AV/B/C Data Sheet Max (V) Max (V) Min (V) 0. 0.40 CCO 5.5 0. 0.20 CCO 0. 0.40 CCO 5.5 0. 0.20 CCO 0. 0.40 CCO 3.6 0. 0.20 CCO 0. 0.45 CCO 3.6 0. 0.20 CCO 0. 0.45 CCO 3.6 0. 0.20 CCO 5 ...

Page 10

... Lattice Semiconductor ispGAL22V10AV/B/C External Switching Characteristics Param Description 1 Output Switching Propagation Delay Output Switching Propagation Delay t Clock to Output Delay Clock to Feedback Delay CF t Setup Time, Input or Feedback before CLK↑ Hold Time, Input or Feedback after CLK↑ H Maximum Clock Frequency with External Feedback, ...

Page 11

... Note: Open drain timing is the same as corresponding LVCMOS timing. Over Recommended Operating Conditions -23 Min. Max. — 0.6 — 0.6 — 0.6 — 0 — 0.6 — 0.2 — 0.2 — 0.1 — 0 — 0.2 — 1.0 11 ispGAL22V10AV/B/C Data Sheet -28 -5 -75 Min. Max. Min. Max. Min. — 0.6 — 0.6 — — 0.6 — 0.6 — — 0.6 — 0.6 — — 0 — 0 — ...

Page 12

... Lattice Semiconductor Switching Waveforms Figure 7. ispGAL22V10AV/B/C Switching Waveforms Combinatorial Output INPUT or I/O FEEDB ACK CO MB INA Input or I/O to Output Enable/Disable INPUT or I/O FEEDBACK t dis OUTPUT Synchronous Preset INPUT or I/O FEEDBACK DRIVING CLK REGISTERED OUTPUT Clock Width CLK ...

Page 13

... Lattice Semiconductor f Descriptions MAX Figure 8. ispGAL22V10AV/B fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK LOGIC REGISTER ARRAY fmax with No Feedback Note: fmax with no feedback may be less than 1/twh + twl ...

Page 14

... I/O I/O 23 I/O TMS TDO Vcco 21 I/O I ispGAL22V10AV/B/C Data Sheet Test Point Input Output 2 Timing Ref. Timing Ref. 1.5V 1.5V 1. CCO (V/B) 0. CCO ( CCO Hi-Z + 0.3 Hi ...

Page 15

... Low 3.3 7.5ns Low 3.3 5.0ns Low 3.3 7.5ns Low 2.5 5.0ns Low 2.5 7.5ns Low 2.5 5.0ns Low 15 ispGAL22V10AV/B/C Data Sheet Grade C = Commercial I = Industrial Package J = PLCC (28 pins QFN (32 pins Lead Free QFN (32 pins) Power L = Low Power Package Pin Count Grade QFN 32 QFN 32 QFN 32 PLCC 28 PLCC ...

Page 16

... Low Lead-Free Commercial t Power PD 3.3 2.3ns Low 3.3 5.0ns Low 3.3 7.5ns Low Lead-Free Industrial t Power PD 3.3 5.0ns Low 3.3 7.5ns Low 16 ispGAL22V10AV/B/C Data Sheet Package Pin Count Grade PLCC 28 QFN 32 QFN 32 PLCC 28 PLCC 28 Package Pin Count Grade QFN 32 QFN 32 QFN 32 Package Pin Count Grade ...

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