ispgal22lv10 Lattice Semiconductor Corp., ispgal22lv10 Datasheet
ispgal22lv10
Manufacturer Part Number
ispgal22lv10
Description
In-system Programmable Low Voltage E2 Cmos Pld Generic Array Logic?
Manufacturer
Lattice Semiconductor Corp.
Datasheet
1.ISPGAL22LV10.pdf
(13 pages)
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• IN-SYSTEM PROGRAMMABLE
• HIGH PERFORMANCE E
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE
• ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS
• COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES
• E
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
The ispGAL22LV10 is manufactured using Lattice Semiconductor's
advanced 3.3V E
Electrically Erasable (E
ispGAL22LV10 can interface with both 3.3V and 5V signal levels.
The ispGAL22LV10 is fully function/fuse map compatible with the
GAL
metric compatible with the GAL22LV10. The ispGAL22LV10 also
shares the same 28-pin PLCC package pin-out as the GAL22LV10.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 10,000 erase/write cycles
and data retention in excess of 20 years are specified.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
isp22lv_06
Features
Description
— IEEE 1149.1 Standard TAP Controller Port
— 4-Wire Serial Programming Interface
— Minimum 10,000 Program/Erase Cycles
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3 ns Maximum from Clock Input to Data Output
— UltraMOS
— JEDEC-Compatible 3.3V Interface Standard
— 5V Tolerant Inputs and I/O
— I/O Interfaces with Standard 5V TTL Devices
— Function/Fuse-Map Compatible with 22LV10/22V10
— Parametric Compatible with 22LV10
— In-System Programmable Logic
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Software-Driven Hardware Configuration
2
CELL TECHNOLOGY
®
Programming
Devices
22LV10 and GAL22V10. Further, the ispGAL22LV10 is para-
®
Advanced CMOS Technology
2
CMOS process, which combines CMOS with
2
) floating gate technology.
2
CMOS
®
TECHNOLOGY
The
1
TMS
Functional Block Diagram
Pin Configuration
TDO
TMS
TCK
TDI
I
I
I
I
I
I
11
5
7
9
12
4
In-System Programmable Low Voltage
ispGAL22LV10
PROGRAMMING
I/CLK
E
LOGIC
2
Top View
I
I
I
I
I
I
I
I
I
I
I
CMOS
14
2
PLCC
ispGAL
28
16
®
PLD Generic Array Logic™
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
TDO
I/O/Q
I/O/Q
I/O/Q
I/CLK
®
GND
TMS
TCK
PRESET
22LV10
RESET
10
12
14
16
16
14
12
10
I
I
I
I
I
I
I
I
I
I
8
8
1
7
14
December 1999
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
Top View
22LV10
ispGAL
SSOP
28
22
15
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
TDO
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
TDI
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