mt8889csr1

Manufacturer Part Numbermt8889csr1
DescriptionIntegrated Dtmf Transceiver With Adaptive Micro Interface
ManufacturerZarlink Semiconductor
mt8889csr1 datasheet
 


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Features
Central office quality DTMF transmitter/receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
D/A
TONE
Converters
Tone Burst
Gating Cct.
IN+
+
Dial
Tone
-
High Group
IN-
Filter
GS
Low Group
OSC1
Oscillator
Circuit
OSC2
Bias
Circuit
V
V
V
DD
Ref
SS
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8889CE
MT8889CS
MT8889CN
MT8889CE1
MT8889CS1
MT8889CN1
MT8889CPR
MT8889CSR
MT8889CSR1
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
Row and
Transmit Data
Column
Register
Counters
Status
Register
Control
Logic
Control
Register
Digital
Filter
Algorithm
and Code
Converter
Register
Filter
Control
Receive Data
Steering
Logic
Register
Logic
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Data Sheet
September 2005
Ordering Information
20 Pin PDIP
Tubes
20 Pin SOIC
Tubes
24 Pin SSOP
Tubes
20 Pin PDIP*
Tubes
20 Pin SOIC*
Tubes
24 Pin SSOP*
Tubes
28 Pin PLCC
Tape & Reel
20 Pin SOIC
Tape & Reel
20 Pin SOIC*
Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Data
Bus
Buffer
Interrupt
Logic
A
Control
I/O
Control
B
D0
D1
D2
D3
IRQ/CP
DS/RD
CS
R/W/WR
RS0

mt8889csr1 Summary of contents

  • Page 1

    ... MT8889CN MT8889CE1 MT8889CS1 MT8889CN1 MT8889CPR MT8889CSR MT8889CSR1 The receiver section is based upon the industry standard MT8870 DTMF receiver while the transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing ...

  • Page 2

    ... D1 18 OSC2 TONE 15 10 IRQ/CP 14 R/W/WR 11 DS/ RS0 24 PIN SSOP Figure 2 - Pin Connections Description /2 Zarlink Semiconductor Inc. Data Sheet • VRef VSS OSC1 OSC2 PIN PLCC Ω ...

  • Page 3

    ... The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. MT8889C Description frees the device to accept a new tone pair. The GT output acts to TSt /2. Provision is made for connection of a feedback resistor to the op Zarlink Semiconductor Inc. Data Sheet detected TSt ...

  • Page 4

    ... Figure 4 - Differential Input Configuration F F DIGIT LOW HIGH 697 1209 1 697 1336 2 697 1477 3 770 1209 4 770 1336 5 770 1477 6 Table 1 - Functional Encode/Decode Table 4 Zarlink Semiconductor Inc. IN+ IN Ref MT8889C IN+ IN Ref MT8889C ...

  • Page 5

    ... 1633 1633 1633 reaches the threshold (V GTP continues to drive high as long as ESt remains high. Finally, after Zarlink Semiconductor Inc. Data Sheet ...

  • Page 6

    ... decreasing tGTP; (tGTP < tGTA (R1C1 GTP C1 GTA (R1R2) / ( decreasing tGTA; (tGTP > tGTA) Figure 6 - Guard Time Adjustment 6 Zarlink Semiconductor Inc. Data Sheet ) TSt - TSt - TSt / TSt - TSt / ...

  • Page 7

    ... The call progress tone input and DTMF input are common REC ID TONE TONE # GTP t GTA t PStRX # n t PStb3 Figure 7 - Receiver Timing Diagram 7 Zarlink Semiconductor Inc. Data Sheet is the minimum signal duration REC with a long t REC TONE # TSt # ( GTP DO ...

  • Page 8

    ... TIME TO DETECT VALID FREQUENCIES PRESENT TIME TO DETECT VALID FREQUENCIES ABSENT GUARD TIME, TONE PRESENT. GTP t GUARD TIME, TONE ABSENT. GTA MT8889C 0 250 500 FREQUENCY (Hz) = Reject = May Accept = Accept Figure 8 - Call Progress Response Figure 9 - Description of Timing Events 8 Zarlink Semiconductor Inc. Data Sheet 750 ...

  • Page 9

    ... Figure 6 that the distortion products are very low in amplitude. MT8889C and f ) are referred to as Low Group and LOW HIGH Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 10 - Spectrum Plot 9 Zarlink Semiconductor Inc. Data Sheet ...

  • Page 10

    ... Refer to Control Register B description for details. ACTIVE INPUT Table 2 - Actual Frequencies Versus Standard Requirements MT8889C OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL L1 697 699.1 L2 770 766.2 L3 852 847.4 L4 941 948.0 H1 1209 1215.9 H2 1336 1331.7 H3 1477 1471.9 H4 1633 1645.0 10 Zarlink Semiconductor Inc. Data Sheet %ERROR +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0.73 ...

  • Page 11

    ... The total 2f nf and the sum of all the intermodulation components. The IMD .... IMD Zarlink Semiconductor Inc. Data Sheet correspond to the low group H ...

  • Page 12

    ... CRB, and subsequent write cycles will be directed back to CRA. The read- only status register indicates the current transceiver state (see Table 8). MT8889C MT8889C MT8889C OSC1 OSC2 OSC1 OSC2 Figure 13 - Common Crystal Connection 12 Zarlink Semiconductor Inc. Data Sheet ...

  • Page 13

    ... Data Register Read from Receive Data Register Write to Control Register Read from Status Register Table 3 - Internal Register Functions IRQ CP/DTMF Table 4 - CRA Bit Positions C/R S/D TEST Table 5 - CRB Bit Positions 13 Zarlink Semiconductor Inc. Data Sheet b0 TOUT b0 BURST ENABLE ...

  • Page 14

    ... After writing to control register B, the following control register write cycle will be directed to control register A. Table 6 - Control Register A Description MT8889C MT8889 MC68HC11 A8-A15 AS AD0-AD3 DS RW 8031/8051 MT8889 8080/8085 A8-A15 ALE DESCRIPTION 14 Zarlink Semiconductor Inc. Data Sheet MT8889C CS D0-D3 RS0 DS/RD R/W/WR MT8889C CS D0-D3 RS0 DS/RD R/W/WR (b) ...

  • Page 15

    ... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 8 - Status Register Description 15 Zarlink Semiconductor Inc. Data Sheet STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode ...

  • Page 16

    ... The performance of the MT8889C can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. TEST POINT MMD7000 (or equivalent) Figure 16 - Test Circuits 16 Zarlink Semiconductor Inc. Data Sheet µP or µ ...

  • Page 17

    ... Figure 17 - Application Notes 17 Zarlink Semiconductor Inc. Data Sheet Data ...

  • Page 18

    ... OZ V 2.4 2.5 2.6 Ref -1.4 -6 2.0 4 -0.5 -3 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units 6 V -0 -65 +150 1000 mW Units Test Conditions 5.25 V °C +85 MHz Units Test Conditions Note 9* V Note =5V ...

  • Page 19

    ... Max. -29 +1 27.5 869 ) unless otherwise stated ‡ Sym. Min. Typ. Max ±1.5%± 2Hz ±3.5% -16 - Zarlink Semiconductor Inc. Data Sheet Units Test Conditions mA V =0. unless otherwise stated 0V Units Test Conditions ≤ V ≤ MΩ ...

  • Page 20

    ... PSE V -6.1 -2.1 HOUT V -8.1 -4.1 LOUT THD -35 ±0.7 ±1 Zarlink Semiconductor Inc. Data Sheet ), unless otherwise stated. Units Conditions Hz @ -25 dBm, Note -25 dBm Hz @ -25 dBm dBm Units Conditions Units Conditions ms Note 11 ms Note 11 µs See Figure 7 µ ...

  • Page 21

    ... DHR t 100 DDR t 45 DSW t 10 DHW CSS t 40 CSH OUT 21 Zarlink Semiconductor Inc. Data Sheet Units Conditions MHz ns Ext. clock % Ext. clock pF ), unless otherwise stated. SS Units Conditions MHz Figure 18 ns Figure 18 ns Figure 18 ns Figure 18 ns Figure 18 ns Figures 19 & ...

  • Page 22

    ... DS falling edge; t DSW MT8889C t CYC Figure 18 - DS/RD/WR Clock Pulse t RWS 16 bytes of Addr t CSS CSS is from DS rising edge to CS rising edge CSH 22 Zarlink Semiconductor Inc. Data Sheet RWH t DDR t DHR t t DSW DHW t CSH CSH ...

  • Page 23

    ... D0-D3 (Addr ALE.Addr * microprocessor pins Figure 21 - 8031/8051/8085 Read Timing Diagram MT8889C t RWS t DDR AS Addr Addr CSH High Byte of Addr t CSS t CSS t t DDR AH A8-A15 Address t CSH 23 Zarlink Semiconductor Inc. Data Sheet t RWH t DHR Data Data t t DSW DHW t DHR Data ...

  • Page 24

    ... ALE P0* (RS0, A0-A7 D0-D3 (Addr ALE.Addr * microprocessor pins Figure 22 - 8031/8051/8085 Write Timing Diagram MT8889C t CSS t DSW t AH Data A8-A15 Address t CSH 24 Zarlink Semiconductor Inc. Data Sheet t DHW ...

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  • Page 28

    ... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...