mt8889csr1 Zarlink Semiconductor, mt8889csr1 Datasheet - Page 13

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mt8889csr1

Manufacturer Part Number
mt8889csr1
Description
Integrated Dtmf Transceiver With Adaptive Micro Interface
Manufacturer
Zarlink Semiconductor
Datasheet

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A software reset must be included at the beginning of all programs to initialize the control registers upon power-up
or power reset (see Figure 17). Refer to Tables 4-7 for bit descriptions of the two control registers.
The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when
the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a
square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external
pull-up resistor (see Figure 15).
RS0
0
0
1
1
RSEL
C/R
b3
b3
Table 3 - Internal Register Functions
Motorola
R/W
0
1
0
1
Table 4 - CRA Bit Positions
Table 5 - CRB Bit Positions
Zarlink Semiconductor Inc.
S/D
IRQ
b2
b2
WR
MT8889C
0
1
0
1
Intel
13
RD
1
0
1
0
CP/DTMF
Write to Transmit
Data Register
Read from Receive
Data Register
Write to Control Register
Read from Status Register
TEST
b1
b1
FUNCTION
ENABLE
BURST
TOUT
b0
b0
Data Sheet

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