mt88l89asr1 Zarlink Semiconductor, mt88l89asr1 Datasheet
mt88l89asr1
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mt88l89asr1 Summary of contents
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... MT88L89AS MT88L89ANR1 24 Pin SSOP* Tubes MT88L89AS1 MT88L89ANR MT88L89ASR MT88L89ASR1 20 Pin SOIC* The receiver section is based upon the industry standard MT8870 DTMF receiver. The transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing ...
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... OSC2 TONE 15 10 IRQ/CP R/W/ DS/ RS0 24 PIN SSOP Figure 2 - Pin Connections Description /2 Zarlink Semiconductor Inc. Data Sheet • VRef VSS 7 23 OSC1 OSC2 PIN PLCC ...
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... MT88L89 Description frees the device to accept a new tone pair. TSt generator. In addition, the IRQ, TONE output and DATA pins are held in Ref /2. Provision is made for connection of a feedback resistor to the op Zarlink Semiconductor Inc. Data Sheet TSt ...
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... FOR UNITY GAIN R5=R1 MT88L89 MT88L89 IN+ IN Ref Figure 3 - Single-Ended Input Configuration C1 MT88L89 IN IN Ref VOLTAGE GAIN (A diff) = R5/R1 V INPUT IMPEDANCE 2 (Z diff (1/ωC) IN Figure 4 - Differential Input Configuration 4 Zarlink Semiconductor Inc. Data Sheet 2 ...
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... 1633 1633 1633 LOGIC LOW, 1= LOGIC HIGH ), v reaches the threshold ( the steering logic to register the tone c GTP TSt 5 Zarlink Semiconductor Inc. Data Sheet ...
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... REC DPmax GTPmax DAmin ≤ REC DPmin GTPmin DAmax ≥ DAmax GTAmax DPmin ≤ DAmin GTAmin DPmax 6 Zarlink Semiconductor Inc. Data Sheet ) TSt - TSt - TSt / TSt t t < ) GTP GTA - TSt / ...
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... Register IRQ/CP MT88L89 REC ID TONE TONE # GTP t GTA t PStRX # n t PStb3 Figure 7 - Receiver Timing Diagram 7 Zarlink Semiconductor Inc. Data Sheet is the minimum signal duration REC with a long t REC TONE # TSt # ( GTP DO ...
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... Hz. Typically, the high group to low group amplitude ratio (twist compensate for high group attenuation on long loops. MT88L89 Figure 8 - Description of Timing Events LOW 8 Zarlink Semiconductor Inc. Data Sheet and f ) are referred to as Low Group HIGH ...
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... Figure 9 shows that the distortion products are very low in amplitude. MT88L89 Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz Figure 9 - Spectrum Plot -25 0 250 500 FREQUENCY (Hz) = Reject = May Accept = Accept Figure 10 - Call Progress Response 9 Zarlink Semiconductor Inc. Data Sheet 750 ...
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... THD (%) = 100 MT88L89 Output Frequency (Hz) Specified Actual L1 697 699.1 L2 770 766.2 L3 852 847.4 L4 941 948.0 H1 1209 1215.9 H2 1336 1331.7 H3 1477 1471.9 H4 1633 1645 fundamental Equation 1. THD (%) For a Single Tone 10 Zarlink Semiconductor Inc. Data Sheet %Error +0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 +0. .... V nf ...
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... IMD .... + IMD Equation 2. THD (%) For a Dual Tone MT88L89 OSC1 OSC2 OSC1 OSC2 Figure 11 - Common Crystal Connection 11 Zarlink Semiconductor Inc. Data Sheet and V correspond to the low group MT88L89 ...
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... Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13 and Figure 14). MT88L89 8xL5x MT88L89 CS A8-A15 D0-D3 ALE RS0 P0 DS/RD RD R/W/ Zarlink Semiconductor Inc. Data Sheet MT88L89 CS D0-D3 RS0 DS/RD R/W/WR 12 (b) Intel ...
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... Write to Transmit Data Register 1 0 Read from Receive Data Register 0 1 Write to Control Register 1 0 Read from Status Register IRQ CP/DTMF TOUT Table 4 - CRA Bit Positions S/D RxEN BURST ENABLE Table 5 - CRB Bit Positions Description 13 Zarlink Semiconductor Inc. Data Sheet ...
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... Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal. Table 8 - Status Register Description 14 Zarlink Semiconductor Inc. Data Sheet Status Flag Cleared Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. ...
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... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT88L89 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 15 Zarlink Semiconductor Inc. Data Sheet ...
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... Microprocessor based systems can inject undesirable noise into the supply rails. The performance of the MT88L89 can be optimized by keeping noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 15 - Application Notes 17 Zarlink Semiconductor Inc. Data Sheet Data ...
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... Sym. Min. Typ. I 2.0 DDQ 3.0 I 2.0 DDTX I 3.0 DDRX I 3 0.7 V IHO DD V ILO V 0.43 0.46 0.51 V TSt Zarlink Semiconductor Inc. Data Sheet Min. Max. 5 -0 -65 +150 1000 Max. Units Test Conditions 3.6 V °C +85 3.583124 MHz Max. Units Test Conditions µA 15.0 Vdd = 2.7V 15.0 Vdd = 3.6V ...
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... Max. I 100 PSRR 50 CMRR VOL fc 0 100 LGS R 50 LGS 19 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions V No load V No load µ load kΩ Note µ µ ...
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... Voltages are with respect to ground (V ‡ Sym. Min. Typ. f 320 540 HR -30 20 Zarlink Semiconductor Inc. Data Sheet = 25° Units Test Conditions Load pp DD Note 9 ) unless otherwise stated. SS Units Notes* ...
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... RWS t 26 RWH DHR t 125 DDR 21 Zarlink Semiconductor Inc. Data Sheet Units Conditions ms Note 11 ms Note 11 µs Figure 7, Note 9 µs Figure 7, Note 9 ms DTMF mode ms DTMF mode ms Call Progress mode ms Call Progress mode dBm R =10kΩ ...
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... DHW t 45 CSS t 10 CSH RDS, DSS ± 1. ± 2%) ≥ 1000 Zarlink Semiconductor Inc. Data Sheet ), unless otherwise stated. SS Max. Units Conditions ns Figures 17 Figures 17 Figures Figures Figures 17 ...
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... AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) Addr * non-mux AS.Addr * microprocessor pins Figure 17 - Motorola BUS Timing Diagram MT88L89 RWS t DDR AS Addr Addr CSH High Byte of Addr t CSS 23 Zarlink Semiconductor Inc. Data Sheet t RWH t DHR Data Data t t DSW DHW ...
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... RD must be high on the falling edge of CS for Intel Bus Timing MT88L89 t CSS DDR AH Data A8-A15 Address t CSH Figure 18 - Intel Read Timing Diagram t CSS DSW t AH Data A8-A15 Address t CSH Figure 19 - Intel Write Timing Diagram 24 Zarlink Semiconductor Inc. Data Sheet t DHR DHW ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...