le79128 Zarlink Semiconductor, le79128 Datasheet
le79128
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le79128 Summary of contents
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... All AC, DC, and signaling parameters are programmable. The Le79128 device is provided with extensive software and support, through the LineCare™ software suite, enabling the designer to develop a fully programmable solution in the least amount of time. ...
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... SPI1 and SPI2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 PCM Interface .43 The VCP Device Interrupt Report and Service Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Timing Diagram Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Troubleshooting at Initial Start-up .47 Physical Dimensions .48 128-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 144-Pin LBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Version 1 to Version .50 Le79128 2 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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... PCS/ PRD PWR 30 PD15 31 PD14 Le79128 Figure 1. Le79128KVC 128-Pin TQFP Package 128-Pin TQFP Microsemi Corporation - CMPG Preliminary Data Sheet AUXOUT 95 UARTRX ...
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... Figure 2. ZL79128GDG2 144-Pin LBGA Diagram Le79128 BOTTOM VIEW 4 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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... TMS F6 DVDD5 C7 F7 DVSS8 TRST C8 EE1 GPIO12 F9 DVSS11 C10 UARTRX F10 TSCXB C11 UARTTX F11 GPIO3 C12 CONF2 F12 GPIO4 Le79128 LBGA Pin Name Pin # G1 DVSS1 G2 GPIO21 G3 DVDD1 G4 VDD18_1 VDD18_3 DVSS12 G10 VDD18_6 G11 GPIO1 G12 GPIO2 ...
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... PIN DESCRIPTIONS Refer to the Next Generation Carrier Chipset Hardware Design Guide (Document ID 126583) for an Application Circuit and Parts List of external components. All signals are CMOS levels unless otherwise stated. Table 2. Le79128 VCP Device Pin Description (Host Interface Pins) Pin Name TQFP LBGA ...
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... Slave PCM Highway B is required for 128 channel operation. Slave PCM Highway B is programmed by selecting VP_OPTION_HWY_B from the API. Refer to the Next Generation Carrier Chipset Hardware Design Guide for diagrams on supported PCM Highway usage. Table 4. Le79128 VCP Device Pin Description (Debug and Development Ports) TQFP LBGA ...
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... Table 5. Le79128 VCP Device Pin Description (Peripheral Logic Pins) TQFP LBGA Pin Name (Alternate) Pin # Pin # SPI1_CLK 58 K10 SPI1_MOSI 54 M10 SPI1_MISO 52 L10 SPI2_CS 41 K9 SPI2_CLK 38 K8 SPI2_MOSI 43 M9 SPI2_MISO 45 L9 GPIO0 (MINT0/TIMER0) 76 H10 GPIO1 (MINT1/TIMER1) 77 G11 GPIO2 (MINT2) 78 G12 GPIO3 (MINT3) ...
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... Table 5. Le79128 VCP Device Pin Description (Peripheral Logic Pins) (Continued) TQFP LBGA Pin Name (Alternate) Pin # Pin # AUXOUT 96 L7 Table 6. Le79128 VCP Device Pin Description (Power Supply Pins) TQFP LBGA Pin Name Pin # Pin # Type PLL_VDD 115 A6 Supply PLL_VSS 114 B7 Ground ...
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... Table 7. Le79128 VCP Device Pin Description (Control Pins) Pin Name TQFP Pin # LBGA Pin # RST 21 H1 WDT_OUT 18 J1 11, 14, 47, A4, A12, B4, RSVD 48, 60, 61, B12, E1, F1, 97, 116, 117 L8, M7, M8 E5, E6, E7, E8, F5, F8, NC 16, 93 G5, G7, G8, H5, H6, H7, H8, J10 Note: 1. Logic state after reset. ...
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... In the case where +3.3 V supply and +1.8 V supply ramps and sequence can not be guaranteed, Ω TRST is typically tied low via resistor to ground. Le79128 Absolute Maximum Ratings can cause permanent device failure. Functionality at or –40 ºC to +85 º +3.3 V ± ...
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... Applies to all digital input pins. 3. Applies to all digital pins with no pull-up, pull-down or keeper. 4. Applies to all digital pins with pull-up, pull-down or keeper. 5. Applies to all digital output pins external DC loads present. Le79128 Condition Min – 0.5 2.0 – 0.5 1.1 – DVDD, outputs in high-Z state. ...
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... Options are selected via the configuration pins, refer to Peripheral Interface (SPI) implements a 4-wire synchronous serial slave interface. The NG chipset (Le79271 SLIC, Le79238 SLAC, and Le79128 VCP) supports use of the GPI 16-bit interface. Refer to the Next Generation Carrier Chipset Hardware Design Guide for connection diagrams. ...
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... One exception is the direct page, which can be accessed at any time without changing the page register. 127 Offset Address 0 Le79128 Figure 4. Host Bus Interface Address Model 120 - 127 Reserved Notes: 16-Bit 1. Page 255 is reserved for loading code. ...
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... Continue Paged Access is the same as the Start Paged Access, except that access starts from where the last paged access left off. By using this command, packets of arbitrary length can be supported. This gives the host the flexibility to split packets transfer into smaller sizes if desired. Le79128 provides a list of transport commands followed by a short description of each Command Bit Position ...
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... The commands are not affected by endianness; their order must be maintained per documentation. Hence, little-endian systems will need to re- verse the command structure. NOP A command is reserved to serve as a NOP. Note that all commands except for the Offset Access commands are implemented by reserving an address from the direct page. Le79128 PG_SEL [7:0] Page addressed by any non-direct HBI access ...
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... Boot Sense (High) Boot Sense (Low) Reset Type Entry Address (High) ENT_ADDR Entry Address (Low) Le79128 Register Description Used by VpGetEvent() to get the next event from the queue. Used by VpGetEvent() to get the next event’s parameter. Allows for interleaved page accesses. Not used by the VP-API ...
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... D14 D7 D6 This register returns the parameter for the last interrupt read from the INTIND register updated whenever the INTIND register is read. Reading this register does not change the state of the interrupt hardware. INT_PARAM[15:0] Le79128 D13 D12 D11 INT_IND[14:8] INT_IND[7:0] Interrupt source bit ...
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... Writing any bit has no affect. 0: Host owns associated mailbox. 1: DSP owns associated mailbox. Page 255 Checksum High Register D15 D14 D13 Microsemi Corporation - CMPG Le79128 Direct page address 0x02 (RW) D12 D11 D10 PG_OFFSET[7:0] Direct page address 0x03 (RW) D12 ...
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... Auto-detected Redundant Highway. 0: Autodetect disabled. PCLKB_FREQ[12:0] should be set by the user. 1: Autodetect the frequency of PCLKB based on the FSB period and store result in PCLKB_FREQ[12:0]. When high the auto detection is restarted and the Microsemi Corporation - CMPG Le79128 Direct page address 0x05 (RW) D12 D11 D10 ...
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... Autodetect disabled. PCLKA_FREQ[12:0] should be set by the user. 1: Autodetect the frequency of PCLKA based on the FSA period and store result in PCLKA_FREQ[12:0]. When High, the auto detection is restarted and the PCLKA_FREQ field is initialized (default). Microsemi Corporation - CMPG Le79128 PCLKB = 512 kHz. PCLKB = 1.536 MHz PCLKB = 2.048 MHz. PCLKB = 4.096 MHz. ...
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... No Failure 1: Clock failure detected CFAIL_PCLKB: PCLKB clock failure indicator. (RO Failure Microsemi Corporation - CMPG Le79128 PCLKA = 512 kHz. PCLKA = 1.536 MHz PCLKA = 2.048 MHz. PCLKA = 4.096 MHz. PCLKA = 8.192 MHz. PCLKA = 16.384 MHz. PCLKA = 35.328 MHz ADSL clock PCLKA = 38.880 MHz (default) ...
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... CURRENT_HIWAY: REFCLK_FREQ: (RO) Note: The power-up default for the 16-bit portion of this register is 0x12FB. Le79128 1: Clock failure detected Power up reset indication. This bit is set by a POR event. It can be cleared by writing 0 to it. This bit is cleared by firmware during the boot sequence so that subsequent POR events can be detected. See Table 11 ...
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... INT pin. This feature allows fewer host inter- ruption from the lower priority events. MOVL: Interrupt Queue Overflow mask. When asserted the interrupt is masked. Microsemi Corporation - CMPG Le79128 Direct page address 0x0C (RO) D12 D11 D10 ...
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... D6 D5 RSVD A four-bit value indicating the cause of the last System Reset event. The Boot Loader copies CLKSTAT [19:16] into the low nibble of this register. See Table 12 for interpretation of these bits. Microsemi Corporation - CMPG Le79128 Direct page address 0x14 (RW) D12 D11 D10 D4 D3 ...
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... The first byte of the sequence (or after a break in the sequence of 128 blocks) must have the PADDR signal asserted. Any Microsemi provided image will conclude with the Page 255 Checksum register returning the value AA55 AA55. This register should be verified by the Host before proceeding. Le79128 D13 D12 ...
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... The host reads the event queue through the interrupt indication and parameter registers. Events are composed of a 16-bit indication value that includes channel and event type fields, and an optional 16-bit parameter. Several of the Le79128 VCP events require a 32-bit timestamp. The timestamp can be reduced to 16-bits by creating a timestamp rollover event, and letting the host maintain the upper 16-bits. An event reports the lower 16-bits of the timestamp in the parameter register. (See the VP-API II User’ ...
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... D14 D7 D6 RSVD RSVD Read GPISTATUS with PADDR High. PAGENUM: Le79128 Description GPI Chip Select (active Low) GPI Address Pin (Command or Data Indicator) GPI Wait (Programmable polarity and drive mode, external pull-inactive required) GPI Data Bus. Alternate configuration as 8-bit Data Bus. ...
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... Figure 5. GPI Connections Using Separate Read and Write Strobes External Processor Chip_Select Figure 6. GPI Connections Using Combined Read/Write and Data Strobes External Processor Chip_Select Read/Write Data_Strobe Le79128 Command in progress. INT logic state. PWAIT logic state. Access Type 0 write data 1 read data ...
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... This is the time between the read command and the first data word. If PWAIT is not used, then the maximum value must be met by the host. If PWAIT is used, faster transactions can occur. Le79128 Figure 9 and Table 15. The 8-bit accesses using a combined read/ ...
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... Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) Figure 8. GPI 16-Bit Read Access Using Separate Read and Write Strobes PCS PWR PRD PWAIT PADDR PD[15:0] Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) Le79128 CMD2 ...
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... Figure 10. GPI 8-Bit Read Access Using Separate Read and Write Strobes PCS 1 2 PWR 3 PRD PWAIT PADDR PD[7:0] CMD1_1 CMD1_2 Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) Le79128 DATA1_1 DATA1_1 32 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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... Figure 11. GPI 8-Bit Write Access Using Combined Read/Write and Data Strobes PCS 1 2 PRD/WR 3 PDS 6 PADDR 7 PD[7:0] CMD1_1 Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) Le79128 Parameter Min 100 — — 0 — ...
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... Figure 12. GPI 8-Bit Read Access Using Combined Read/Write and Data Strobes PCS 1 2 PRD/WR 3 PDS PWAIT PADDR PD[7:0] CMD1_1 CMD1_2 Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) Le79128 DATA1_1 34 Microsemi Corporation - CMPG Preliminary Data Sheet 1 ...
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... CMD1 CMD_STAT1 Note: Each Write and Read access is qualified by an active chip select strobe. (Chip select can be tied Low in some applications.) PD[7:0] CMD1_1 PD[15:0] CMD1 Bits 7:0 Data Bytes swapped Le79128 4 CMD_STAT2 Figure 14. GPI Data Byte Swap Access CMD1_2 DATA1 Bits 15:8 35 Microsemi Corporation - CMPG ...
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... SO on the falling edge of the clock. Figure 15 shows the SPI interface system with a 4-wire SPI master. When the VCP device supports command framing on the SS pin, a 3-wire interface as shown in Figure 16, on page 37 Le79128 VCP Le79128 Description SPI clock SPI slave input/master output ...
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... Le79128 VCP SPI Features In order to connect to different SPI masters and share the same logic view with the General Purpose Parallel Interface, the SPI slave of the VCP device has the following designs: • Separate SI and SO pins. • No read latency: no latency between the read command word and the first data word. ...
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... Bits 7:0 of the data word comes out first and bits 15:8 of the data word come out second. The timing information for the read/write command is in Figure 18. One Data Word Write in Byte Framing Mode SS SCK or SCK SI cmd_wd[15:8] SO Le79128 Figure 17. SS Framing Modes cmd_wd[7:0] data_wd[15:8] Byte framing mode data word Word framing mode data word Command framing mode Figure 19 ...
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... Figure 19. One Data Word Read in Word Framing Mode SS SCK or SCK command word SI SO Figure 20. One Data Word Write in Byte Framing Mode with Byte Swap SS SCK or SCK SI cmd_wd[15:8] SO Microsemi Corporation - CMPG Le79128 . . . . data word cmd_wd[7:0] data_wd[7:0] 39 Preliminary Data Sheet data_wd[15:8] ...
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... SCK cycles. During command framing mode held Low for the whole duration of the command. Besides, multiple commands can be transferred with SS low for the whole duration of the multiple commands. The rising edge of the SS indicates the end of the command sequence and resets the SPI slave. 6. Pin loading is assumed 75pF load Le79128 1 Parameter Min — ...
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... SS 10 Data SI Valid V IH SCK Data Three-State OH SO Valid V OL Le79128 Figure 21. SPI Interface (Input Timing Data Data Valid Valid Figure 22. SPI Interface (Output Timing Data Data Valid Valid 41 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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... Refer to Figure 26 for timing diagram test points. 2. Assumes 40-pF load on SPI_CLK, SPI_MOSI, and SPI2_CS or GPIO[31:16]. 3. Assumes 150-pF load on SPI_CLK and SPI_MOSI, but 40-pF load on SPI2_CS or GPIO[31:16]. Assumes a 50 output of SPI_CLK. Timing Requirements SPI_CLK 4 SPI2_CS/GPIO[31:16]) 6 MOSI 8 MISO Le79128 1 Parameter Min 114 34 77 — — — — ...
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... PCM INTERFACE Two PCM blocks reside on the Le79128 device. There is a Slave PCM Highway A/Redundant block comprised of the PCLKA, FSA, DXA, DRA, TSCXA, TSCRA, PCLKB, FSB, DXB, DRB, TSCXB, and TSCRB pins, and a block used as the Slave PCM Highway B comprised of the MPCLK, MFS, MDX, and MDR pins. The Slave PCM Highway A/Redundant block requires PCLKA or PCLKB as inputs ...
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... TSCXA/B (Transmit on Positive PCLK Edge) *Because the receive sampling point is defined from the rising edge, the clock duty cycle may affect timing relative to the negative edge of the clock Le79128 Ω series termination at output of MPCLK. Figure 24. PCM Highway Timing 5 ...
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... Interrupts are reported based on their priority. System interrupts have the highest priority. For the event interrupts, event queue 1 has the highest priority and event queue 3 has the lowest priority. The interrupt signal is latched before reporting to the host through the INT pin. Le79128 45 Microsemi Corporation - CMPG ...
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... KΩ resistor. This will allow easy access if it becomes necessary to jumper to the Debug port. Figure 25. VCP Debug Port - Optional Header Interface TDI TDO TCK Le79128 VCP TMS TRST TIMING DIAGRAM TEST POINTS DVDD = PLL_VDD = 3.3 V +5%, PLL_VSS = DVSS = 0 V. 2.4 V 0.4 V Le79128 +3 Debug 10K 33 Header ...
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... It also verifies basic call control, usage of profiles, DTMF decoding, and line testing. The boot-load is supplied as a binary firmware load to the VCP boot-loaded into the VCP along with some C host code to boot-load and control the image. Le79128 47 Microsemi Corporation - CMPG ...
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... PHYSICAL DIMENSIONS 128-Pin TQFP Le79128 48 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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... Parallelism measurement shall exclude any effect of mark on top surface of package. UNIT MM Note: Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the device. Markings will vary with the mold tool used in manufacturing. Le79128 144 LBGA Min Max 1.25 1.60 ...
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... Page 11; Operating Ranges description, changed reliability reference document from "section 4.6.2 of Bellcore TR-TSY- 000357" to "Telcordia GR-357-CORE". • Page 12; DC Specifications, No. 2 & 4, changed Max Input High Voltage from "3.465 V" to "3.6 V". • Page 26; Code Loading, Table 12, changed Pin terminology to agree with Pin Name in Table 5. Le79128 50 Microsemi Corporation - CMPG Preliminary Data Sheet ...
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