mt8981de1 Zarlink Semiconductor, mt8981de1 Datasheet
mt8981de1
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mt8981de1 Summary of contents
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... Ordering Information MT8981DE MT8981DP MT8981DPR MT8981DP1 MT8981DPR1 44 Pin PLCC* MT8981DE1 Description This VLSI ISO-CMOS device is designed for switching PCM-encoded voice or data, under microprocessor control modern digital exchange, PBX or Central Office. It provides simultaneous connections for up to 128 64 kbit/s channels. Each of the four serial inputs and outputs consist kbit/s channels multiplexed to form a 2048 kbit/s ST-BUS stream ...
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... Chip Select (Input). This is the input for the active low chip select on the microprocessor interface. MT8981D 39 STo3 VSS Figure 2 - Pin Connections Description . DD 2 Zarlink Semiconductor Inc. Data Sheet DTA 2 39 STi0 ODE 3 38 STo0 STi1 STi2 4 37 STo1 5 STi3 36 STo2 6 35 STo3 ...
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... ST-BUS input channels or check which switched connections have already been established. By integrating both switching and interprocessor communications, the MT8981 allows systems to use distributed processing and to switch voice or data in an ST-BUS architecture. MT8981D Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Connection Memory Low. The Connection Memory High determines whether individual output channels are in Message Mode, and allows individual output channels to go into a high-impedance state, which enables arrays of MT8981s to be constructed. It also controls the CSTo pin. All ST-BUS timing is derived from the two signals C4i and F0i. MT8981D 4 Zarlink Semiconductor Inc. Data Sheet ...
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... MT8981D A0 HEX ADDRESS • • • • • • • • • Figure 3 - Address Memory Map 5 Zarlink Semiconductor Inc. Data Sheet LOCATION Control Register * † Channel 0 † Channel 1 • • • † Channel 31 ...
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... The number expressed in binary notation on these bits refers to the input or output ST-BUS stream Address Bits which corresponds to the subsection of memory made accessible for subsequent operations. MT8981D (unused) Memory (unused) Select Bits Description Figure 4 - Control Register Bits 6 Zarlink Semiconductor Inc. Data Sheet Stream Address Bits 1 0 ...
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... Per Channel - These bits give 0s if read. Control Bits Description Figure 5 - Connection Memory High Bits Stream Channel Address Address Bits Bits Description Figure 6 - Connection Memory Low Bits 7 Zarlink Semiconductor Inc. Data Sheet ...
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... MT8981D STo0 STi0 Filter/Codec D C STo0 STi0 Line Interface Circuit with 8964 Filter/Codec System originating from the bottom MT8981, which generates the C 8 Zarlink Semiconductor Inc. Data Sheet , and ST- R MT8964 Line Driver and Wire Converter Signalling Logic ...
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... Repeated for Lines 2 to 127 STi0-3 4 Line Interface Circuit with Codec (e.g. 8964) 8981 #1 STi0/3 STo0/3 8981 #2 STi0/3 STo0/3 8981 #3 STi0/3 STo0/3 8981 #4 STi0/3 STo0/3 9 Zarlink Semiconductor Inc. Data Sheet Line 1 • • • Repeated for Lines 2 to 127 Line 128 OUT 0/3 OUT 4/7 ...
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... Delay through the address decoder requires the VMA signal to be used twice to remove glitches. The MEK6802D3 board uses a 10 KΩ pullup on the MR pin, which would have to be incorporated into the circuit if the board was replaced by a processor. MT8981D 10 Zarlink Semiconductor Inc. Data Sheet ...
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... STo0 STo1 STo2 STo3 STo4 STo5 STo6 STo7 0V VSS 510 Ω DTA CS 0V C4i 0V F0i 0V 0V 100pF 11 Zarlink Semiconductor Inc. Data Sheet 5V A15 1 16 A14 A13 HCT 0V 5 138 VMA ...
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... Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 -0 °C -65 +150 unless otherwise stated. Test Conditions ° Units ...
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... CTT t 20 200 FPS t 0.020 50 FPH t 244 FPW Bit o Figure 12 - Frame Alignment 13 Zarlink Semiconductor Inc. Data Sheet open circuit except DD when testing output levels or high impedance states switched when testing output SS levels or high impedance states. SS Units ...
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... OED XCH t 75 110 XCD t -40 -20 SIS t 90 SIH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet FPS t FPH Units Test Conditions KΩ*, C =150 =150 =150 pF ...
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... MT8981D Bit Cell Boundary 2.0V C4i 0.8V t SOH 2.4V STo0 to 0.4V STo3 STo0 2. STo3 0.4V STo0 2.4V to 0.4V STo3 Figure 14 - Serial Outputs and External Control 2.0V ODE 0.8V 2.4V STo0 * to STo3 0.4V t OED Figure 15 - Output Driver Enable 15 Zarlink Semiconductor Inc. Data Sheet * t SAZ t SZA t SOH t SAA * ...
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... DHT RDZ t 0 CSH t 0 RWH t 0 ADH AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet t SIH Units Test Conditions =150 cycles C4i cycles ns 1 cycles C4i cycles 1 cycles ...
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... DS 0.8V 2.0V CS 0.8V t CSS 2.0V R/W 0.8V t RWS 2. 0. ADS 2.4V * DTA 0.4V 2.4V (Read) 2.0V (Write 0.8V (Read 0.8V (Write MT8981D t AKD t RDS t FWS SWD Figure 17 - Processor Bus 17 Zarlink Semiconductor Inc. Data Sheet t CSH t RWH t ADH t AKH * t DHT * t RDZ ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...