mt8985apr1 Zarlink Semiconductor, mt8985apr1 Datasheet
mt8985apr1
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mt8985apr1 Summary of contents
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... Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved. CMOS ST-BUS MT8985AE MT8985AP MT8985AL MT8985APR MT8985AP1 MT8985APR1 44 Pin PLCC* MT8985AE1 MT8985AL1 Switch (DX pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital ...
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... R PIN PLASTIC DIP Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. Data Sheet Change 1 33 STo3 2 32 STo4 3 31 STo5 4 30 STo6 5 29 STo7 6 28 VSS ...
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... CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. 6, 18, 12, Connection. 28, 34 MT8985 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Data memory at the selected address are then transferred to the parallel to serial converters. By having the output channel to specify the input channel through the connect memory, the user can route the same input channel to several output channels, allowing broadcasting facility in the switch. MT8985 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode: MT8985 5 Zarlink Semiconductor Inc. Data Sheet ...
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... DTA output provides a maximum acknowledgement delay of 800 ns for read/write operations in the Connection Memory. However, for operations in the Data Memory (Message Mode), the maximum acknowledgement delay can be 1220 ns. MT8985 Output Channel Throughput Delay m=n, n+1 or n+2 m timeslots m>n+2 m-n time slots m<n 32-(n-m) time slots 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Channel 31 Figure 3 - Address Memory Map 7 Zarlink Semiconductor Inc. Data Sheet • • • • • ...
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... MT8985 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. MT8985 MS1 MS0 STA2 DESCRIPTION Figure 4 - Control Register Bits 8 Zarlink Semiconductor Inc. Data Sheet 1 0 STA1 STA0 ...
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... ODE signal high to relinquish high impedance state control to the CMH MT8985 V DESCRIPTION Figure 5 - Connection Memory High Bits SAB1 SAB0 CAB4 CAB3 CAB2 DESCRIPTION Figure 6 - Connection Memory Low Bits 9 Zarlink Semiconductor Inc. Data Sheet 1 0 CSTo CAB1 CAB0 0s. b ...
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... Basic Rate Line Card MT8930/31 S/U MT8910 MT8972 Figure 7 - Typical Exchange, PBX or Multiplexer Configuration MT8985 To other lines Layers 2 & 3 Entity ST-BUS To other lines ROUTING MATRIX MT8985’s MT8940/ MT8941 µC Primary Rate Card 10 Zarlink Semiconductor Inc. Data Sheet ST-BUS ST-BUS T1/E1 Link MH89760/ MH89790 MT8920 ...
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... ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface. MT8985 ISDN Desktops (2B+D) • • • • • • Server 2 Server Server 3 Server 4 Isochronous Network 11 Zarlink Semiconductor Inc. Data Sheet Connections (e.g. Video) ...
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... ISDN S-Interface • • • • • MVIP BUS MT8985 MT8985 MT8985s (x4) MT8985 MT8985 HDLC • • • • • To Video, Data, Fax Services Public Local Environment Network Access 12 Zarlink Semiconductor Inc. Data Sheet Server 3 T1 ST-BUS MH89760B MH89790B E1 Dual T1/E1 Card ...
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... Input Streams From MVIP 8 Input On-Board ST-BUS Streams Figure 9 - 512-Channel Switch Array MT8985 MT8985 #1 CSTo MVIP Direction MT8985 #2 CSTo MVIP Enable MT8985 #3 MT8985 #4 13 Zarlink Semiconductor Inc. Data Sheet 8 Output Streams to MVIP 8 Output On-Board ST-BUS Streams ...
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... SWITCH MT8985 T1/E1 MH89760B SWITCH MT8985 or MH89790B HDLC MT8952B ANALOG D-PHONE MT8992/93 PC INTERFACE Figure 10 - Dual T1/E1 Card Functional Block Diagram Zarlink Semiconductor Inc. MT8985 MVIP HEADER MVIP STi0-7 512 Channel SWITCH Switch Matrix MT8985 SWITCH MT8985 DPLL MT8941 14 Data Sheet FDL HDLC MT8952B ...
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... MT8985 MVIP HEADER MVIP STo1-7 STi7-1 SWITCH MT8985 STi0 S INTERFACE HDLC MT8930B DIGITAL PHONE HDLC MT8992/93 PC INTERFACE Figure 11 - S-Access Card Functional Block Diagram 15 Zarlink Semiconductor Inc. MVIP STi1-7 STo7-1 MATRIX STo0 DPLL MT8941 DTMF RECEIVER MT8870 Data Sheet ...
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... 100 2 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 -0 °C -65 +150 unless otherwise stated. Units Test Conditions ° ...
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... ± =5V 5%, V =0V Zarlink Semiconductor Inc. Data Sheet S1 is open circuit except when testing output levels or high impedance states switched when testing output SS levels or high impedance states. Units Test Conditions ns ns ...
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... F0iS t 20 F0iH t 45 DAA t 20 STiS t 20 STiH ± =5V 5%, V =0V Zarlink Semiconductor Inc. Data Sheet Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Ch. 0 Bit 6 Bit 5 Max. Units Test Conditions 300 ns 150 ns ns ...
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... Sym. Min. Typ. Max. t 100 SAZ t 100 SZA t OED t 0 XCD , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet bit 2 bit 3 t C4i Units Test Conditions KΩ*, C =150 =150 KΩ ...
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... MT8985 Bit Cell Boundary 2.0V C4i 0.8V STo0 2.4V to STo7 0.4V t 2.4V STo0 * to STo7 0.4V 2.4V CSTo 0.4V Figure 15 - Serial Outputs and External Control 2.0V ODE 0.8V STo0 2. STo7 0. OED OED Figure 16 - Output Driver Enable 20 Zarlink Semiconductor Inc. Data Sheet (GCI) (ST-BUS) * SAZ t SZA t XCD * ...
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... SWD t 8 DHW t AKD 560 1220 300/370 730/800 155 110 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 KΩ*, L C =150 ...
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... DS 0.8V 2.0V CS 0.8V 2.0V R/W 0.8V 2.0V A0-A6 0.8V 2.0V D0-D7 READ 0.8V 2.0V D0-D7 WRITE 0.8V 2.0V DTA 0.8V Figure 17 - Motorola Non-Multiplexed Bus Timing MT8985 t CSS t RWS t ADS VALID DATA t t SWD DSW VALID DATA t DDR t AKD 22 Zarlink Semiconductor Inc. Data Sheet t CSH t RWH t ADH t DHR t DHW t AKH ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...