mt8977ac Mitel, mt8977ac Datasheet

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mt8977ac

Manufacturer Part Number
mt8977ac
Description
Iso-cmos St-bus ?amily T1/esf Framer Circuit
Manufacturer
Mitel
Datasheet
Features
Applications
ACCUNET
CSTi0
CSTi1
DSTo
CSTo
RxSF
TxSF
DSTi
D3/D4 or ESF framing and SLC-96 compatible
Two frame elastic buffer with jitter tolerance
improved to 156 UI
Insertion and detection of A, B, C, D bits,
signalling freeze, optional debounce
Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
Yellow alarm and blue alarm signal capabilities
Bipolar violation count, F
error count
Selectable robbed bit signalling
Frame and superframe sync. signals, Tx and Rx
AMI encoding and decoding
Per channel, overall, and remote loop around
Digital phase detector between T1 line and ST-
BUS
One uncommitted scan point and drive point
Pin compatible with MT8976 and MT8979
ST-BUS compatible
DS1/ESF digital trunk interfaces
Computer to PBX interfaces (DMI and CPI)
High speed computer to computer data links
XCtl
XSt
C2i
F0i
®
T1.5 is a registered trademark of AT & T
Circuitry
ST-BUS
Timing
Interface
Interface
Control
Data
Serial
Control Logic
T
error count, CRC
Elastic Buffer
Figure 1 - Functional Block Diagram
2048-1544
Converter
2 Frame
Signalling RAM
with Slip
Control
ABCD
T1/ESF Framer Circuit (ACCUNET
ISO-CMOS ST-BUS
Description
The MT8977 is a variant of the MT8976 framer,
which has been enhanced to meet ACCUNET
wander tolerance (138 UI).
The MT8977 meets ESF and D3/D4 formats, and is
compatible with SLC-96 systems.
Interface
DS1
Link
Detector
MT8977AC
MT8977AE
MT8977AP
Phase
Ordering Information
Counter
-40 C to 85 C
DS1
Preliminary Information
28 Pin Ceramic DIP
28 Pin Plastic DIP
44 Pin PLCC
Remote &
ISSUE 2
Loopbacks
Digital
FAMILY
MT8977
C1.5i
RxFDLClk
E1.5i
E8Ko
RxFDL
V
V
RxA
RxB
TxA
TxB
TxFDLClk
TxFDL
RxD
SS
DD
May 1995
®
T1.5)
T1.5
4-99

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mt8977ac Summary of contents

Page 1

... Control Logic XSt ® ACCUNET T1 registered trademark of AT & T ISO-CMOS ST-BUS T1/ESF Framer Circuit (ACCUNET MT8977AC MT8977AE MT8977AP Description The MT8977 is a variant of the MT8976 framer, which has been enhanced to meet ACCUNET wander tolerance (138 UI). The MT8977 meets ESF and D3/D4 formats, and is compatible with SLC-96 systems ...

Page 2

MT8977 ISO-CMOS 1 TxA 28 VDD 2 TxB DSTo 26 F0i E1.5i 5 RxA 24 C1. RxB RxSF 7 RxD 22 TxSF 8 CSTi1 21 C2i 9 TxFDL 20 RxFDL 10 TxFDLClk ...

Page 3

Preliminary Information Pin Description (Continued) Pin # Name DIP PLCC 12 19 CSTi0 Control ST-BUS Input #0. A 2048 kbit/s serial control stream that contains 24 per channel control words and two master control words E8Ko Extracted 8 ...

Page 4

MT8977 ISO-CMOS Functional Timing Diagrams C2i DSTi DSTo CSTi0/CSTi1 CSTo E1. INT DATA DS1 AMI LINE SIGNAL RxA RxB RxD E8Ko C1.5i INT DATA TxA TxB DS1 AMI LINE SIGNAL 4-102 125 ...

Page 5

Preliminary Information MT8977 ISO-CMOS 4-103 ...

Page 6

... MT8977 via 2048 kbit/s serial streams conforming to Mitel’s ST-BUS format. The ST-BUS is a TDM serial bus that operates at 2048 kbits/s. The serial streams are divided into 125 µsec frames that are made bit channels. ...

Page 7

Preliminary Information Bit Name 7 Debounce When set the received and D signalling bits are reported directly in the per channel status words output at CSTo. When clear, the signalling bits are debounced for ...

Page 8

MT8977 ISO-CMOS Bit Name 7 RMLOOP Remote Loopback. When set, the data received at RxA and RxB is looped back to TxB and TxA respectively. The data is clocked into the device with E1.5i. The device still monitors the received ...

Page 9

Preliminary Information Frame # FPS FDL CRC CB1 CB2 CB3 CB4 ...

Page 10

MT8977 ISO-CMOS Frame † Resynchronization ...

Page 11

Preliminary Information Bipolar Violation Counter The Bipolar Violation bit in Master Status Word 1 will toggle after 256 violations have been detected in the received signal. It has a maximum refresh time of 96 ms. This means that the bit ...

Page 12

MT8977 ISO-CMOS Bit Name 7 YLALR Yellow Alarm Indication. This bit is set when the chip is receiving bit position 2 of every DS0 channel. 6 MIMIC This bit is set if the frame search algorithm found ...

Page 13

Preliminary Information Received Signalling Bits The and D signalling bits are output from the device in the 24 Per Channel Status Words. Their location in the serial steam output at CSTo is shown in Figure 6 and ...

Page 14

MT8977 ISO-CMOS Write Pointer 386 Bit 47 CH Elastic Store 34 CH Figure 8 - Elastic Buffer Functional Diagram (156 UI Wander Tolerance) decrease over time. When this delay approaches the minimum two channel threshold, the ...

Page 15

Preliminary Information Hunt Mode Candidate Candidate Verify Candidate In sync New Frame Position * Note: Only when in ESF mode and CRC option is enabled. Figure 9 - Off-Line Framer State Diagram discovered. It is, therefore, possible that the device ...

Page 16

MT8977 ISO-CMOS 50 Percentage Reframe Time Probability Versus Reframe Time AAA AAA AAA AAA 40 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA % 30 AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA AAA ...

Page 17

Preliminary Information shows the MT8977 interfaced to a parallel bus structure using two STPA‘s operating in modes 1 and 2. The first STPA operating in mode 2 (MMS=0, MS1=1, 24/32=0), routes data information between the parallel telecom bus and the ...

Page 18

MT8977 ISO-CMOS MT8920B (Mode HIGH STo0 SPEED STi0 STo1 PARALLEL TELECOM CS BUS R/W C4i OE F0i MMS MS1 24/32 +5V MT8920B (Mode STo0 A -A ...

Page 19

Preliminary Information Absolute Maximum Ratings* Parameter 1 Power Supplies with respect Voltage on any pin other than supplies 3 Current at any pin other than supplies 4 Storage Temperature 5 Package Power Dissipation * Exceeding these values ...

Page 20

MT8977 ISO-CMOS AC Electrical Characteristics Characteristics 1 C2i Clock Period 2 C2i Clock Width High or Low 3 Frame Pulse Setup Time 4 Frame Pulse Hold Time 5 Frame Pulse Width 6 RxSF Output Delay 7 TxSF Hold Time 8 ...

Page 21

Preliminary Information AC Electrical Characteristics Characteristics 1 E1.5i Clock Period 2 E1.5i Clock Width High or Low † Timing is over recommended temperature & power supply voltage ranges. ‡ Typical figures are at 25°C and are for design aid only; ...

Page 22

MT8977 ISO-CMOS AC Electrical Characteristics Parameters 1 External Control Delay 2 External Status Setup Time 3 External Status Hold Time 4 8 kHz Output Delay 5 8 kHz Output Low Width 6 8 kHz Output High Width 7 8 kHz ...

Page 23

Preliminary Information AC Electrical Characteristics Parameters 1 Transmit Steering Delay 2 Transmit Steering Transition Time 3 Received Steering Setup Time 4 Received Steering Hold Time 5 Received Data Setup Time 6 Received Data Hold Time 7 C1.5i Period 8 C1.5i ...

Page 24

MT8977 ISO-CMOS AC Electrical Characteristics Parameters 1 Transmit FDL Setup Time 2 Transmit FDL Hold Time 3 Receive FDL Output Delay 4 Receive FDL Clock Delay 5 Transmit FDL Clock Delay † Timing is over recommended temperature & power supply ...

Page 25

Preliminary Information CHANNEL CHANNEL • • • • • • • • NB: Numbering BIT 7 differs from Fig 25. Figure 24 - Format of 2048 kbit/s ST-BUS Streams CHANNEL CHANNEL S Bit 24 1 (1/1.544) s NB: ...

Page 26

MT8977 ISO-CMOS Appendix Control and Status Register Summary 7 6 Debounce TSPZCS B8ZS 1 Disabled 1 Disabled 1 B8ZS 0 Enabled 0 Enabled 0 Jammed Bit Master Control Word 1 (Channel 15, CSTi0) RMLOOP DGLOOP ALL 1’s 1 Enabled 1 ...

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