mt89l85apr1 Zarlink Semiconductor, mt89l85apr1 Datasheet

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mt89l85apr1

Manufacturer Part Number
mt89l85apr1
Description
256 X 256 Channels 8 Tdm Streams At 2.048 Mbps 3.3 V Non-blocking Enhance Digital Switch Edx With Constant Delay Mode
Manufacturer
Zarlink Semiconductor
Datasheet
Features
Applications
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
3.3 volt supply
5 V tolerant inputs and TTL compatible outputs
256 x 256 channel non-blocking switch
Programmable frame integrity for wideband
channels
Automatic identification of ST-BUS/GCI interface
backplanes
Per channel tristate control
Patented message mode
Non-multiplexed microprocessor interface
Available in PLCC-44 and SSOP-48 packages
Pin compatible with MT8985 device
Low power consumption
Medium size digital switch matrices
Hyperchannel switching (e.g., ISDN H0)
ST-BUS/MVIP
Serial bus control and monitoring
Centralized voice processing systems
Data multiplexer
** for 48-pin SSOP only
Converter
Parallel
Serial
to
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
interface functions
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Memory
Data
Figure 1 - Functional Block Diagram
DS
C4i
Counter
Frame
Zarlink Semiconductor Inc.
CS
Control Register
Control Interface
F0i
R/W A5/
RESET V
A0
**
1
CMOS ST-BUS
Description
The MT89L85 Enhanced Digital Switch device is an
upgraded 3-volt version of the MT8985 Digital Switch.
It is pin compatible with the MT8985 and retains all of
the MT8985's functionality. The enhanced digital
switch is designed for switching PCM-encoded voice or
data,
exchanges,
environment. It provides simultaneous connections for
up to 256 64 kb/s channels. Each of the eight serial
inputs and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s stream. As the main
function in switching applications, the device provides
per-channel selection between variable or constant
throughput delays. The constant throughput delay
feature allows grouped channels such as ISDN H0 to
be switched through the device maintaining its
sequence integrity. The MT89L85 is ideal for medium
sized mixed voice/data switch and voice processing
applications.
DTA D7/
DD
V
SS
D0
MT89L85AP
MT89L85AN
MT89L85APR
MT89L85ANR
MT89L85AN1
MT89L85ANR1 48 Pin SSOP*
MT89L85AP1
MT89L85APR1 44 Pin PLCC*
under
Connection
PBXs
microprocessor
Memory
TM
CSTo
Output
Enhanced Digital Switch
MUX
Ordering Information
*Pb Free Matte Tin
Family
44 Pin PLCC
48 Pin SSOP
44 Pin PLCC
48 Pin SSOP
48 Pin SSOP*
44 Pin PLCC*
-40°C to +85°C
and
Converter
any
Parallel
Serial
control,
ODE
to
Tubes
Tubes
Tape & Reel
Tape & Reel
Tubes
Tape & Reel
Tubes
Tape & Reel
ST-BUS/MVIP
Data Sheet
MT89L85
February 2006
in
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
digital

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mt89l85apr1 Summary of contents

Page 1

... MT89L85AN MT89L85APR MT89L85ANR MT89L85AN1 MT89L85ANR1 48 Pin SSOP* MT89L85AP1 MT89L85APR1 44 Pin PLCC* Description The MT89L85 Enhanced Digital Switch device is an upgraded 3-volt version of the MT8985 Digital Switch pin compatible with the MT8985 and retains all of the MT8985's functionality. The enhanced digital ...

Page 2

... V F0i C4i R/W (JEDEC MO-118, 300mil Wide) Figure 2 - Pin Connections Description 2 Zarlink Semiconductor Inc. Data Sheet 1 48 CSTo 2 ODE STo0 4 45 STo1 5 STo2 STo3 STo4 STo5 ...

Page 3

... MT89L85 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock for the device is 4.096 MHz, as required in ST-BUS and GCI specifications. MT89L85 Description 3 Zarlink Semiconductor Inc. Data Sheet ...

Page 4

... The MT89L85 frame synchronization pulse can be formatted according to ST-BUS or GCI interface specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT89L85 device automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial MT89L85 4 Zarlink Semiconductor Inc. Data Sheet ...

Page 5

... Likewise, the maximum delay is achieved when the first time slot in a frame (channel 0) is switched to the last time slot in the frame (channel 31), resulting in 94 time slots of delay. MT89L85 Output Throughput Delay Channel n m=n, n timeslots n+2 n m>n+2 m-n time slots n m<n 32-(n-m) time slots 5 Zarlink Semiconductor Inc. Data Sheet ...

Page 6

... Channel 31 Figure 3 - Address Memory Map 6 Zarlink Semiconductor Inc. Data Sheet • • • • • ...

Page 7

... Care should be taken that no two connected ST-BUS outputs drive the bus simultaneously. When this process is complete, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the CMH MT89L85 7 Zarlink Semiconductor Inc. Data Sheet 0s. b ...

Page 8

... Stream Address Bits 2-0. The number expressed in binary notation on these bits refers to the input or output ST-BUS stream which corresponds to the subsection of memory made accessible for subsequent operations Don’t care MT89L85 MS1 MS0 STA2 Description Figure 4 - Control Register Bits 8 Zarlink Semiconductor Inc. Data Sheet 1 0 STA1 STA0 ...

Page 9

... MT89L85 V Description Figure 5 - Connection Memory High Bits SAB1 SAB0 CAB4 CAB3 CAB2 Description Figure 6 - Connection Memory Low Bits 9 Zarlink Semiconductor Inc. Data Sheet 1 0 CSTo CAB1 CAB0 ...

Page 10

... Basic Rate Line Card MT8930/31 S/U MT8910 MT8972 Figure 7 - Typical Exchange, PBX or Multiplexer Configuration MT89L85 To other lines Layers 2 & 3 Entity ST-BUS To other lines ROUTING MATRIX MT89L85’s MT8940/ MT8941 µC Primary Rate Card 10 Zarlink Semiconductor Inc. Data Sheet ST-BUS ST-BUS T1/E1 Link MH89760/ MH89790 MT8920 ...

Page 11

... ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface. MT89L85 ISDN Desktops (2B+D) • • • • • • Server Server 3 Isochronous Network Figure 8a - Private Isochronous Network 11 Zarlink Semiconductor Inc. Data Sheet Server Connections (e.g. Video) Server 4 ...

Page 12

... ISDN S-Interface • • • • • MVIP BUS MT89L85 MT89L85 MT89L85s (x4) MT89L85 MT89L85 HDLC • • • • • To Video, Data, Fax Services Public Local Environment Network Access 12 Zarlink Semiconductor Inc. Data Sheet Server 3 T1 ST-BUS MH89760B MH89790B E1 Dual T1/E1 Card ...

Page 13

... Input Streams From MVIP 8 Input On-Board ST-BUS Streams Figure 9 - 512-Channel Switch Array MT89L85 MT89L85 #1 CSTo MVIP Direction MT89L85 #2 CSTo MVIP Enable MT89L85 #3 MT89L85 #4 13 Zarlink Semiconductor Inc. Data Sheet 8 Output Streams to MVIP 8 Output On-Board ST-BUS Streams ...

Page 14

... FDL HDLC MT8952B SWITCH MT89L85 T1/E1 MH89760B SWITCH MT89L85 or MH89790B HDLC MT8952B ANALOG D-PHONE MT8992/93 PC INTERFACE Figure 10 - Dual T1/E1 Card Functional Block Diagram Zarlink Semiconductor Inc. MVIP STi0-7 512 Channel SWITCH Switch Matrix MT89L85 SWITCH MT89L85 DPLL MT8941 14 Data Sheet FDL HDLC MT8952B T1/E1 MH89760B or ...

Page 15

... MT89L85 MVIP HEADER MVIP STo1-7 STi7-1 SWITCH MT89L85 STi0 S INTERFACE HDLC MT8930B DIGITAL PHONE HDLC MT8992/93 PC INTERFACE Figure 11 - S-Access Card Functional Block Diagram 15 Zarlink Semiconductor Inc. MVIP STi1-7 STo7-1 MATRIX STo0 DPLL MT8941 DTMF RECEIVER MT8870 Data Sheet ...

Page 16

... Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 5 -0 °C -55 +125 unless otherwise stated. Units Test Conditions ° Units Test Conditions ...

Page 17

... STiH t 200 244 300 C4i t 85 122 150 122 150 ± =5V 5%, V =0V, T =– Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Test Conditions =150 ° C). ...

Page 18

... F0iS t 20 F0iH t DAA t 20 STiS t 20 STiH ± =3.3V 5%, V =0V, T =– Zarlink Semiconductor Inc. Data Sheet Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Ch. 0 Bit 6 Bit 5 Max. Units Test Conditions 300 ns 150 ns ns ...

Page 19

... Sym. Min. Typ. Max SAZ t 55 SZA t 50 OED t 55 XCD , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet bit 2 bit 3 t C4i Units Test Conditions KΩ*, C =150 =150 KΩ ...

Page 20

... HM to STo7 STo0 STo7 CSTo V LM Figure 14 - Serial Outputs and External Control V HM ODE V LM STo0 STo7 OED OED Figure 15 - Output Driver Enable 20 Zarlink Semiconductor Inc. Data Sheet (GCI) (ST-BUS) * SAZ t SZA t XCD * ...

Page 21

... SWD DHW t AKD 560 1220 62/30 120/ 120 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 KΩ*, L C =150 ...

Page 22

... A0-A6 D0-D7 READ D0-D7 WRITE DTA Figure 16 - Motorola Non-Multiplexed Bus Timing MT89L85 t CSS t RWS t ADS VALID DATA t t DSW SWD VALID DATA t t DDR DHW t AKD 22 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH ...

Page 23

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Page 24

... Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...

Page 25

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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