zl30100 Zarlink Semiconductor, zl30100 Datasheet
zl30100
Available stocks
Related parts for zl30100
zl30100 Summary of contents
Page 1
... Corrector Circuit DPLL TIE Mode Corrector Control Enable Feedback Frequency Select MUX HOLDOVER Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30100 Data Sheet October 2004 Ordering Information 64 pin TQFP -40qC to +85qC OUT_SEL C2o C4/C65o C8/C32o E1 C16o Synthesizer F4/F65o F8/F32o F16o DS1 C1 ...
Page 2
... The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable ...
Page 3
... Time Interval Error (TIE 5.11 Maximum Time Interval Error (MTIE 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ZL30100 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
Page 4
... Figure 11 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12 - Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13 - Clock Oscillator Circuit Figure 14 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ZL30100 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
Page 5
... Table “Performance Characteristics*: Output Jitter Generation - ITU-T G.812 Conformance“ 32 Table “Performance Characteristics* - Unfiltered Intrinsic Jitter“ ZL30100 Change Jitter changed to 0.6 ns from 0.5 ns Added note specifying not e-Pad Added information about Schmitt trigger feedback paths to C1.5o, C2o, C16o, and F8/F32o Added text about input pulse width restriction Added details to " ...
Page 6
... REF1 NC IC OOR_SEL TIE_CLR BW_SEL Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30100 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30100 does not use the e-Pad TQFP. ZL30100 ...
Page 7
... ZL30100 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on this pin will cause the ZL30100 to measure a new delay for its TIE corrector circuit thereby minimizing the output phase movement when it transitions from Holdover or Freerun mode to Normal mode ...
Page 8
... Analog Ground AGND Analog Ground C4/C65o Clock 4.096 MHz or 65.536 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbps, 4.096 Mbps or 65.536 MHz (ST-BUS 65.536 Mbps). The output frequency is selected via the OUT_SEL pin. ZL30100 Description nominal. DC nominal. DC nominal. DC nominal. ...
Page 9
... MHz, 8.192 MHz or 16.384 MHz. This pin is internally pulled down to GND internal bonding Connection. Leave unconnected. 57 REF1 Reference (Input). See REF0 pin description internal bonding Connection. Leave unconnected. ZL30100 Description nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...
Page 10
... Reference Select Multiplexer (MUX) The ZL30100 accepts two simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE corrector circuit based on the reference selection (REF_SEL) input. ...
Page 11
... When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. ZL30100 OR dis/requalify timer ...
Page 12
... This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover mode. ZL30100 C20 -83 -64 ...
Page 13
... Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30100 is always hitless unless TIE_CLR is kept low continuously. ...
Page 14
... Phase = 10 x (300 ns changes where: - 0.15 ppm is the accuracy of the Holdover mode - the maximum phase discontinuity in the transition from the Normal mode to the Holdover mode ZL30100 REF Output Clock REF Output Clock REF Output Clock REF ...
Page 15
... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30100 consists of a phase detector, a limiter, a loop filter, a digitally controlled oscillator (DCO) and a lock indicator, as shown in Figure 9. The data path from the phase detector to the limiter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. ...
Page 16
... As shown in Figure 1, the control state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30100 is based on the inputs MODE_SEL1:0, REF_SEL and HMS. 3.7 Master Clock The ZL30100 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 4.0 Control and Modes of Operation 4 ...
Page 17
... Freerun mode is typically used when an independent clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun mode, the ZL30100 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals. ...
Page 18
... DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 10). If HMS=0 then the ZL30100 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 8). If HMS=1 then the ZL30100 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained ...
Page 19
... Reference Selection The active reference input (REF0, REF1) is selected by the REF_SEL pin as shown in Table 5. If the logic value of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30100 will perform a hitless reference switch. When the REF_SEL inputs are used to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references ...
Page 20
... Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). ZL30100 REF0 REF1 ...
Page 21
... Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30100, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
Page 22
... For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. 6.0 Applications This section contains ZL30100 application specific details for power supply decoupling, reset operation, clock and crystal operation. 6.1 Power Supply Decoupling It is recommended to place a 100 nF decoupling capacitor close to the power and ground pairs as shown in Figure 12 to ensure optimal jitter performance ...
Page 23
... Master Clock The ZL30100 can use either a clock or crystal as the master timing source. Zarlink application note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30100. 6.2.1 Clock Oscillator When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, phase noise, output rise and fall times, output levels and duty cycle ...
Page 24
... ZL30100 6.3 Power Up Sequence The ZL30100 requires that the 3.3 V rail is not powered-up later than the 1.8 V rail. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power up the 3.3 V rail fully first, then power up the 1.8 V rail 2 ...
Page 25
... A simple power up reset circuit with about reset low time is shown in Figure 15. Resistor R only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30100 ZL30100 +3 RST ...
Page 26
... Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated. Recommended Operating Conditions* Characteristics 1 Supply voltage 2 Core supply voltage 3 Operating temperature * Voltages are with respect to ground (GND) unless otherwise stated. ZL30100 Symbol V DD_R V CORE_R V PIN V OSC I ...
Page 27
... Rise and fall threshold voltage low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IF, OF Figure 16 - Timing Parameter Measurement Voltage Levels ZL30100 Sym. Min. Max. I 3.0 6.5 DDS I 32 ...
Page 28
... MHz reference input to F8/F32o delay 8 16.384 MHz reference input to C16o delay 9 16.384 MHz reference input to F8/F32o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. t REF<xx>P REF0/1 output clock with the same frequency as REF F8_32o ZL30100 Symbol t REF8KP t REF1.5P t REF2P t REF8P t REF16P t ...
Page 29
... F65o pulse with low 20 F65o delay 21 C65o pulse width low 22 C65o delay 23 Output clock and frame pulse rise time 24 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30100 Sym. Min. Max. t 323.1 323.7 C1.5L t -0.6 0.6 C1.5D t 243.2 243 ...
Page 30
... C1.5o C2o F4o C4o F8o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure 18 - Output Timing Referenced to F8/F32o ZL30100 t C1.5L t C2L t F4L t C4L t C8L t C16L t C32L t C65L 30 Zarlink Semiconductor Inc ...
Page 31
... Switching from Normal mode to Holdover mode 11 Switching from Holdover mode to Normal mode Output Phase Slope 12 1.8 Hz Filter and 922 Hz Filter * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30100 Sym. Min. Max. Units -32 +32 ppm -50 +50 ppm 40 60 ...
Page 32
... UI filter time domain 0. 0 G.812 ITU-T Jitter Generation Requirements Jitter Equivalent Limit in limit in the UI filter time domain 0. Max. [ns pp 0.45 0.47 0.42 0.42 0.56 0.46 0.49 0.40 0.33 0.43 0.36 0.42 32 Zarlink Semiconductor Inc. Data Sheet ZL30100 maximum jitter Units generation 45.3 0.30 ns 324 0.32 ns ZL30100 maximum jitter Units generation 24.4 0.36 ns Notes ] ...
Page 33
... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
Page 34
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...