zl30105 Zarlink Semiconductor, zl30105 Datasheet
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zl30105 Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA™ and H.110 ZL30105QDG ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack • Less than 0.6 ns clocks and frame pulses • ...
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... SDH and T1/E1 transmission equipment. It provides advanced support for systems deploying redundant clocks. The ZL30105 generates SBI, ST-BUS and other TDM clock and framing signals that are phase locked to one of three network references system master-clock reference. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the master-clock and slave-clock outputs even in the presence of high network jitter ...
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... Time Interval Error (TIE 5.11 Maximum Time Interval Error (MTIE 5.12 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.5 Clock Redundancy System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ZL30105 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ZL30105 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 26 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 27 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure Output Timing Referenced to F8/F32o Figure 29 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 30 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ZL30105 List of Figures 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Table “AC Electrical Characteristics* - Input to output timing for REF0, REF1 and REF2 references when TIE_CLR = 0 (see Figure 26).“ Section 7.2 50 ZL30105 Change Changed description for hitless reference switching. Removed power supply decoupling circuit and included reference to synchronizer power supply decoupling application note. Change ...
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... SEC_MSTR APP_SEL0 TIE_CLR FASTLOCK 64 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) Note 1: The ZL30105 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30105 does not use the e-Pad TQFP. ZL30105 ZL30105 ...
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... Hitless Mode Switching (Input). The HMS input controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. A logic low at this pin will cause the ZL30105 to maintain the delay stored in the TIE corrector circuit when it transitions from Holdover or Freerun mode to Normal mode. A logic high on ...
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... Internal Connection. Leave unconnected. 23 GND Ground APP_SEL1 Application Selection 1 (Input). This input combined with APP_SEL0 selects the application that the ZL30105 is optimized for, see Table 1 on page 20 Positive Supply Voltage. +3 OUT_SEL2 Output Selection 2 (Input). This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 21 ...
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... Reference (Input). This is one of three (REF0, REF1 and REF2) input reference sources used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. This pin is internally pulled down to GND. ZL30105 Description nominal DC ...
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... Reference Select Multiplexer (MUX) The ZL30105 accepts three simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs. ...
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... The single cycle and coarse frequency failures must be absent for let the timer re-qualify the input reference signal as valid. Multiple failures of less than 2.5 s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4 where REF0 experiences disruptions while REF1 is stable. ZL30105 OR REF_OOR OR ...
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... SCM or CFM failure REF0 dis/requalify timer on REF0 2.5 s REF_OOR0 (internal signal) REF_FAIL0 HOLDOVER REF_SEL REF0 REF1 Figure 4 - Behaviour of the Dis/Re-qualify Timer ZL30105 SCM or CFM failure 10 s REF0 13 Zarlink Semiconductor Inc. Data Sheet REF1 ...
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... If there no other reference available, it stays in Holdover mode. The precise frequency monitor’s failure thresholds are selected with the APP_SEL pins based on the ZL30105 applications, see Table 1. Figure 5, Figure 6 and Figure 7 show the out of range limits for various master clock accuracies ...
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... This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it recovers from Holdover mode. ZL30105 C20 -12 -9 ...
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... Normal mode. This causes accumulation of phase in network elements. In both cases the PLL’s output can be aligned with the input reference by setting TIE_CLR low. Regardless of the HMS pin state, reference switching in the ZL30105 is always hitless unless TIE_CLR is kept low continuously. ...
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... Phase = 0.01 ppm holdover_drift - Phase = mode_change - Phase = ns) = 330 ns 10 changes ZL30105 REF Output Clock REF Output Clock REF Output Clock TIE_CLR=0 REF Output ...
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... Digital Phase Lock Loop (DPLL) The DPLL of the ZL30105 consists of a phase detector, a limiter, a loop filter and a digitally controlled oscillator as shown in Figure 11. The data path from the phase detector to the limiter is tapped and routed to the lock detector that provides a lock indication which is output at the LOCK pin. ...
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... As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30105 is based on the inputs MODE_SEL1:0, REF_SEL1:0 and HMS. 3.7 Master Clock The ZL30105 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. ZL30105 19 Zarlink Semiconductor Inc ...
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... Detected REF Frequency 00, 01 00, 01, 10 8.192 MHz, 16.384 MHz, Table 2 - Loop Filter and Limiter Settings ZL30105 Applicable Standard ANSI T1.403 Telcordia GR-1244-CORE Stratum 4/4E ITU-T G.703 ETSI ETS 300 011 Telcordia GR-1244-CORE Stratum 3 ITU-T G.813 Option 1 Telcordia GR-253-CORE Loop Filter Bandwidth ...
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... MODE_SEL1 and MODE_SEL0 as is shown in Table 4. Transitioning from one mode to the other is controlled by an external controller. The ZL30105 can be configured to automatically select a valid input reference under control of its internal state machine by setting MODE_SEL1:0 = 11. In this mode of operation, a state machine controls selection of references (REF0 or REF1) used for synchronization ...
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... DPLL to recover from Holdover via one of two paths depending on the logic level at the HMS pin (see Figure 12). If HMS=0 then the ZL30105 will transition directly to Normal mode and it will align its output signals with its input reference (see Figure 10). If HMS=1 then the ZL30105 will transition to Normal mode via the TIE correction state and the phase difference between the output signals and the input reference will be maintained ...
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... In the manual modes of operation (MODE_SEL1:0 ≠ 11) the active reference input (REF0, REF1 or REF2) is selected by the REF_SEL1 and REF_SEL0 pins as shown in Table 5. When the logic value of the REF_SEL pins is changed when the DPLL is in Normal mode, the ZL30105 will perform a hitless reference switch. REF_SEL1 ...
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... If both references fail then the ZL30105 enters the Holdover mode without switching to another reference. When the ZL30105 comes out of reset or when REF2 is the current reference when the ZL30105 is put in the Automatic mode, then REF0 has priority over REF1. Otherwise there is no preference for REF0 or REF1 which is referred to as non-revertive reference selection ...
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... REF_SEL outputs indicate that the device has remained locked to the old reference. However the LOCK pin is de-asserted, the lock-qualify timer is reset, and the LOCK pin remains de-asserted for the full lock-time duration. See 7.2, “Performance Characteristics“ on page 46 for lock-time duration. ZL30105 Normal (HOLDOVER=0) ...
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... Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Figure 17 illustrates this process. ZL30105 10 s REF1 Lock Time 26 Zarlink Semiconductor Inc ...
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... Therefore the redundant signals must closely track the active signals. The ZL30105 supports this kind of clock redundancy in various ways; • Lock only to the active clock. The ZL30105 uses the 922 Hz loop filter bandwidth to closely track the active clock, even in the presence of jitter on the active clock. However the active and redundant frame pulse may not be aligned. ...
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... REF2_SYNC input. The REF2_SYNC pulse must be generated from the clock that is present on the REF2 input. The ZL30105 checks the number of REF2 cycles in the REF2_SYNC period. If this is not the nominal number of cycles, the REF2_SYNC pulse is considered invalid. For example, if REF2 ...
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... The HOLDOVER and REF_FAIL pins help evaluate quality of clocks and quality of redundant clock. ZL30105 OSC REF0 Output Clocks REF1 ZL30105 REF2 REF2_SYNC Redundant Frame Sync (optional) Redundant Clock Active Clock Active Frame Sync (optional) REF2_SYNC REF2 ZL30105 REF0 Output Clocks REF1 OSC 29 Zarlink Semiconductor Inc. Data Sheet ...
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... REF2 and REF2_SYNC as the input reference, REF_SEL1=1 The ZL30105 allows for the switch from Secondary Master mode to Primary Master mode with no frequency or phase hits on the output clocks. The switch from Primary Master mode to Secondary Master mode may introduce a phase transient on the output clocks as the TIE correction circuit is disabled to allow the Secondary master device to track the active clocks closely ...
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... Holdover accuracy is defined as the absolute accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30105, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. ...
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... Although a short lock time is desirable not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. And better (smaller) phase slope performance (limiter) results in longer lock times. ZL30105 32 Zarlink Semiconductor Inc. ...
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... Tolerance 3 Rise & fall time 4 Duty cycle Table 7 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30105, and the OSCo output should be left open as shown in Figure 20. ZL30105 ZL30105 20 MHz as required < 40% to 60% +3 ...
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... Frequency 2 Tolerance 3 Oscillation mode 4 Resonance mode 5 Load capacitance 6 Maximum series resistance Table 8 - Typical Crystal Oscillator Specification ZL30105 ZL30105 20 MHz as required fundamental parallel as required 50 Ω 20 MHz OSCi 1 MΩ OSCo 100 Ω 1 µH The 100 Ω resistor and the 1 µH inductor may improve stability and are optional ...
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... Power Up Sequence The ZL30105 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power up the 3.3 V supply fully first, then power up the1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1 ...
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... AdvancedTCA compliant system. Timing for these types of systems can be generated by the ZL30105 which supports primary/secondary master timing protection switching. The architecture shown in Figure 23 and Figure 24 is based on the ZL30105 being deployed on two separate timing cards; the primary master timing card and the secondary master timing card. In normal operation the primary master timing card receives synchronization from the network and provides timing for the whole system ...
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... Primary Master Timing Card ZL30105 REF0 REF1 C19o REF2 F8o REF2_SYNC SEC_MSTR 1 Master/Slave Control Secondary Master Timing Card Figure 24 - Typical Clocking Architecture of a PICMG AdvancedTCA™ System ZL30105 Backplane CLK2A CLK1B CLK1A CLK2B ZL30106 Line Card PLL ZL30106 Line Card PLL 37 Zarlink Semiconductor Inc. ...
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... OSCi = Clock, OUT_SEL=000 3 OSCi = Clock, OUT_SEL=111 4 Core supply current with: OSCi = OSCi = Clock 6 Schmitt trigger Low to High threshold point 7 Schmitt trigger High to Low threshold point 8 Input leakage current 9 High-level output voltage ZL30105 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 PIN V -0.3 OSC I PIN T -55 ...
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... MHz reference period 8 reference pulse width high or low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-of-Range limits. ZL30105 Sym. Min. Max. Units V ...
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... Supply voltage and operating temperature are as per Recommended Operating Conditions. * See Figure 18, “Examples of REF2 & REF2_SYNC to Output Alignment” on page 28 for further explanation. REF2 REF2_SYNC Note: REF2 can be 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. REF2_SYNC can be 2 kHz or 8 kHz. ZL30105 t REF<xx> REFW REFW ...
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... MHz reference input to F8/F32o delay 10 16.384 MHz reference input to C16o delay 11 16.384 MHz reference input to F8/F32o delay 12 19.44 MHz reference input to C19o delay 13 19.44 MHz reference input to F8/F32o delay * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30105 Symbol t REF2kD t REF2k_F8D t REF8kD t REF1.5D t REF1 ...
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... F65o pulse with low 18 F65o delay 19 C65o pulse width low 20 C65o delay 21 Output clock and frame pulse rise time 22 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30105 Sym. Min. Max. t -0.4 0.3 C2D t 243.0 244.1 C2L t 243 ...
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... F8o C2o F4o C4o C8o F16o C16o F32o C32o F65o C65o F32o, C32o, F65o and C65o are drawn on a larger scale than the other waveforms in this diagram. Figure Output Timing Referenced to F8/F32o ZL30105 t C2L t F4L t C4L t C8L t C16L t C32L t C65L 43 Zarlink Semiconductor Inc ...
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... F2ko pulse width high 5 Output clock and frame pulse rise time 6 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o C19o F2ko Figure 30 - SDH Output Timing Referenced to F8/F32o ZL30105 Sym. Min. Max. t -0.6 0.6 C1.5D t 323.1 324 ...
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... Output clock and frame pulse rise time 10 Output clock and frame pulse fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. F8_32o C44o C34o C8.4o C6o Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o ZL30105 Sym. Min. Max. t -0.70 0.70 C6D t 78.5 79 ...
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... Holdover stability 3 Freerun accuracy Capture range 4 DS1 / E1 5 PDH Stratum 3 / SDH Reference Out of Range Threshold (including hysteresis) 6 DS1 PDH Stratum 3 / SDH Lock Time 9 DS1 (1.8 Hz filter - all reference frequencies) ZL30105 Min. Max. Units -32 +32 ppm -50 +50 ppm -4.6 +4.6 ppm -4.6 +4.6 ppm ...
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... Normal mode Output Phase Slope 20 DS1 / E1 / PDH Stratum 3 21 SDH 22 SEC_MSTR=1: clock redundancy support * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30105 Min. Max. Units ±100 ppm frequency offset SEC_MSTR = 0, HMS = 1, TIE_CLR = 1, and FASTLOCK=0 ±9.2 ppm frequency offset, ...
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... UI filter time domain 0. Zarlink Semiconductor Inc. Data Sheet Interface DS1 Line timing, DS1 External timing 2048 kbit/s Option 1 ZL30105 maximum jitter Units generation 45.3 0. 324 0. ZL30105 maximum jitter Units generation 7.92 0. ZL30105 maximum jitter Units generation 24.4 0. ...
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... UI 0.96 pp 0.1 UI 0. rms 1.5 UI 9.65 pp ITU-T G.813 Limit in Equivalent limit UI in time domain ( 6.4 ns) 0.1 UI 0.64 pp 0.5 UI 3.22 pp 0 Zarlink Semiconductor Inc. Data Sheet ZL30105 maximum jitter Units generation 0. 0. rms 0. ZL30105 maximum jitter generation Units ...
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... F4o (8 kHz) 16 F8o (8 kHz) 17 F16o (8 kHz) 18 F32o (8 kHz) 19 F65o (8 kHz) * Supply voltage and operating temperature are as per Recommended Operating Conditions. 8.0 References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. ZL30105 Max. Notes [ 0.45 0.47 0.53 0.42 0.58 0.42 0.55 0.56 ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...