zl30109 Zarlink Semiconductor, zl30109 Datasheet

zl30109

Manufacturer Part Number

zl30109

Description

Ds1/e1 System Synchronizer With 19.44 Mhz Output

Manufacturer

Zarlink Semiconductor

Datasheet

1.ZL30109.pdf (37 pages)

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

zl30109QDG1

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ZARLINK

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Features

•

REF_FAIL0

REF_FAIL1

Supports Telcordia GR-1244-CORE Stratum 4 and

Stratum 4E

Supports ITU-T G.823 and G.824 for 2048 kbit/s and

1544 kbit/s interfaces

Supports ANSI T1.403 and ETSI ETS 300 011 for

ISDN primary rate interfaces

Simple hardware control interface

Accepts two input references and synchronizes to

any combination of 2 kHz, 8 kHz, 1.544 MHz,

2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz

inputs

Provides a range of clock outputs: 1.544 MHz,

2.048 MHz, 16.384 MHz, 19.44 MHz and either

4.096 MHz and 8.192 MHz or 32.768 MHz and

65.536 MHz

Hitless reference switching between any

combination of valid input reference frequencies

Provides 5 styles of 8 kHz framing pulses and a

2 kHz multi-frame pulse

Holdover frequency accuracy of 1.5 x 10

Lock, Holdover and selectable Out of Range

indication

Selectable loop filter bandwidth of 1.8 Hz or 922 Hz

OOR_SEL

REF_SEL

REF0

REF1

RST

MODE_SEL1:0

Reference

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

Monitor

MUX

State Machine

OSCi

Master Clock

HMS

Corrector

OSCo

Enable

TIE

Figure 1 - Functional Block Diagram

HOLDOVER

Corrector

TIE_CLR

-7

Circuit

Zarlink Semiconductor Inc.

TIE

Reference

Feedback

Control

Virtual

Mode

•

Applications

•

ZL30109QDG

ZL30109QDG1 64 pin TQFP* Trays, Bake & Drypack

Less than 24 ps

19.44 MHz output clock, compliant with OC-3 and

STM-1 jitter specifications

Less than 0.6 ns

clocks

External master clock source: clock oscillator or

crystal

Synchronization and timing control for DSLAM,

Gateway and PBX systems that require Stratum

4/4E timing

Line Card synchronization for SDH/PDH

applications

Clock and frame pulse source for ST-BUS, GCI

and other time division multiplex (TDM) buses

DS1/E1 System Synchronizer with

BW_SEL

Frequency

Select

DPLL

MUX

LOCK

Ordering Information

64 Pin TQFP Trays, Bake & Drypack

*Pb Free Matte Tin

rms

-40°C to +85°C

Synthesizer

SONET/SDH

OUT_SEL

Synthesizer

TCK

Synthesizer

intrinsic jitter on all output

intrinsic jitter on the

DS1

1149.1a

TDI

IEEE

19.44 MHz Output

TMS

TDO

Data Sheet

ZL30109

November 2005

C2o

C4/C65o

C8/C32o

C16o

F4/F65o

F8/F32o

F16o

C1.5o

C19o

F2ko

TRST

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