zl30119 Zarlink Semiconductor, zl30119 Datasheet

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zl30119

Manufacturer Part Number
zl30119
Description
Low Jitter Line Card Synchronizer
Manufacturer
Zarlink Semiconductor
Datasheet

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A full Design Manual is available to qualified customers.
To
TimingandSync@Zarlink.com.
Features
int_b
Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
Internal APLL provides standard output clock
frequencies from 6.48 MHz up to 622.08 MHz with
jitter less than 1 ps RMS for OC-48/STM-16
interfaces
Programmable output synthesizers (P0, P1)
generate clock frequencies from any multiple of
8 kHz up to 77.76 MHz in addition to 2 kHz
Provides two DPLLs which are independently
configurable through a serial peripheral interface
DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover), and
selectable loop bandwidth
sync0
sync1
sync2
osco
osci
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
register,
sck
Master
Clock
sync2:0
ref7:0
Reference
please
Monitors
SPI Interface
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
trst_b
si
so
tck
IEEE 1449.1
ref_&_sync_status
JTAG
send
tdi tms
cs_b
Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved.
an
tdo
rst_b
dpll2_ref
email
State Machine
Figure 1 - Block Diagram
Controller &
Zarlink Semiconductor Inc.
dpll1_mod_sel1:0
dpll1_hs_en
to
1
ref
ref
sync
Low Jitter Line Card Synchronizer
DPLL2
DPLL1
DPLL2 provides a comprehensive set of features
for generating derived output clocks and other
general purpose clocks
Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
Configurable input to output delay, and output to
output phase alignment
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
ZL30119GGG
ZL30119GGG2
fb_clk/fp
dpll1_lock
*Pb Free Tin/Silver/Copper
Ordering Information
dpll1_holdover
sdh_filter
-40
100 Pin CABGA
100 Pin CABGA*
o
C to +85
SONET/SDH
filter_ref0
Synthesizer
Synthesizer
Synthesizer
Feedback
diff0_en
APLL
P1
P0
o
C
SONET/SDH
filter_ref1
diff1_en
Data Sheet
ZL30119
Trays
Trays
December 2005
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
diff0
diff1
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
fb_clk

Related parts for zl30119

zl30119 Summary of contents

Page 1

... DPLL2 ref ref DPLL1 sync fb_clk/fp Controller & State Machine rst_b dpll1_mod_sel1:0 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. ZL30119 SONET/SDH Data Sheet December 2005 Ordering Information 100 Pin CABGA Trays 100 Pin CABGA* Trays +85 C dpll1_holdover diff0_en ...

Page 2

... Applications TM • AMCs for AdvancedTCA and MicroTCA Systems • Multi-Service Edge Switches or Routers • DSLAM Line Cards • WAN Line Cards • RNC/Mobile Switching Center Line Cards • ADM Line Cards ZL30119 2 Zarlink Semiconductor Inc. Data Sheet ...

Page 3

... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ZL30119 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...

Page 4

... Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ZL30119 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...

Page 5

... Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ZL30119 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...

Page 6

... The default frequency for this frame pulse output is 8 kHz. J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. ZL30119 Description ss. 6 Zarlink Semiconductor Inc. Data Sheet ...

Page 7

... This pin is internally pull up to Vdd. D3 diff1_en I Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the u differential LVPECL output 1 driver is enabled. When set low, the differential driver is tristated reducing power consumption.This pin is internally pull up to Vdd. ZL30119 Description 7 Zarlink Semiconductor Inc. Data Sheet ...

Page 8

... GND. J3 tms I Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of u the TAP controller. This pin is internally pulled then it should be left unconnected. ZL30119 Description 8 Zarlink Semiconductor Inc. Data Sheet . If this pin is not used DD ...

Page 9

... Positive Supply Voltage. +1.8V CORE Positive Analog Supply Voltage. +3. C10 Positive Analog Supply Voltage. +1.8V CORE ZL30119 Description nominal. DC nominal. DC nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet ...

Page 10

... Analog Ground. 0 Volts Input I - Input, Internally pulled down Input, Internally pulled Output A - Analog P - Power G - Ground ZL30119 Description 10 Zarlink Semiconductor Inc. Data Sheet ...

Page 11

... Functional Description The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. ...

Page 12

... The input references are continuously monitored for frequency accuracy and phase regularity least one of the input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given a stable reference input, the ZL30119 will enter in the Normal (locked) mode. Normal (locked) ...

Page 13

... DPLL will align the output frame pulses to the output clock edge that is aligned to the input frame pulse. ZL30119 DPLL2 ref7:0 DPLL1 Figure 3 - Reference and Sync Inputs input is selected with its corresponding ref n ref n ...

Page 14

... Single Cycle Monitor (SCM) The SCM block measures the period of each reference clock cycle to detect phase irregularities or a missing clock edge. In general, if the measured period deviates by more than 50% from the nominal period, then an SCM failure (scm_fail) is declared. ZL30119 2 kHz 8 kHz 64 kHz 1 ...

Page 15

... Output Clocks and Frame Pulses The ZL30119 offers a wide variety of outputs including two low-jitter differential LVPECL clocks (diff0_p/n, diff1_p/n), two SONET/SDH LVCMOS (sdh_clk0, sdh_clk1) output clocks and four programmable LVCMOS (p0_clk0, p0_clk1, p1_clk0, p1_clk1) output clocks. In addition to the clock outputs, two LVCMOS SONET/SDH frame pulse outputs (sdh_fp0, sdh_fp1) and two LVCMOS programmable frame pulses (p0_fp0, p0_fp1) are also available ...

Page 16

... The output clocks and frame pulses derived from the SONET/SDH APLL are always synchronous with DPLL1, and the clocks and frame pulses generated from the programmable synthesizers can be synchronized to either DPLL1 or DPLL2. This allows the ZL30119 to have two independent timing paths. DPLL2 DPLL1 The supported frequencies for the output clocks and frame pulses are shown in Table 4 ...

Page 17

... Configurable Input-to-Output and Output-to-Output Delays The ZL30119 allows programmable static delay compensation for controlling input-to-output and output-to-output delays of its clocks and frame pulses. All of the output synthesizers (SONET/SDH, P0, P1, Feedback) locked to DPLL1 can be configured to lead or lag the selected input reference clock using the DPLL1 Fine Delay. The delay is programmed in steps of 119.2 ps with a range of -128 to +127 steps giving a total delay adjustment in the range of -15 ...

Page 18

... Software Configuration The ZL30119 is mainly controlled by accessing software registers through the serial peripheral interface (SPI). The device can be configured to operate in a highly automated manner which minimizes its interaction with the system’s processor can operate in a manual mode where the system processor controls most of the operation of the device ...

Page 19

... ZL30119 Reset Value (Hex) FF Ref4 and ref5 auto-detected frequency value status register FF Ref6 and ref7 auto-detected frequency value status register EE Sync0 and sync1 auto-detected frequency value and sync failure status register 0E Sync2 auto-detected frequency value and sync ...

Page 20

... ZL30119 Reset Value (Hex) 00 Control register for the ref0 to ref7 enable revertive signals 10 Control register for the ref0 and ref1 priority values 32 Control register for the ref2 and ref3 priority values 54 Control register for the ref4 and re5 priority ...

Page 21

... ZL30119 Reset Value (Hex) 8F Control register to enable p0_clk0, p0_clk1, p0_fp0, p0_fp1, the P0 synthesizer and select the source 0F Control register to generate p0_clk0, p0_clk1, p0_fp0 and p0_fp1 00 Control register for the [7:0] bits of the N of N*8k clk0 01 ...

Page 22

... ZL30119 Reset Value (Hex) C1 Control register for the [7:0] bits of the N of N*8k clk0 00 Control register for the [13:8] bits of the N of N*8k clk0 00 Control register for the p1_clk0 phase position coarse tuning 3F Control register for the p1_clk1 frequency ...

Page 23

... ZL30119 Reset Value (Hex) 00 Bits [15:8] of the programmable frame pulse phase offset in multiples of 1/311.04 MHz 00 Bits [21:16] of the programmable frame pulse phase offset in multiples of 8 kHz cycles Differential Output Configuration A3 Control register to enable diff0, diff1 and ...

Page 24

... Reserved 7F ZL30119 Reset Value (Hex) 00 Control register for the custom configuration A: The [15:0] bits of the single cycle CFM high limiter 00 Control register for the custom configuration A: CFM reference monitoring cycles - 1 00 Control register for the custom configuration ...

Page 25

... References AdvancedTCA, ATCA and the AdvancedTCA and ATCA logos are trademarks of the PCI Industrial Computer Manufacturers Group. This datasheet provides a summary of the high level features of the ZL30119. Refer to the ZL30119 Design Manual for a more complete description. ZL30119 25 Zarlink Semiconductor Inc. Data Sheet ...

Page 26

... Zarlink Semiconductor 2005 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...

Page 27

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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