zl30110 Zarlink Semiconductor, zl30110 Datasheet
zl30110
Available stocks
Related parts for zl30110
zl30110 Summary of contents
Page 1
... Description The ZL30110 clock rate conversion digital phase- locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition ...
Page 2
... IC V LOCK REF_FAIL GND GNDV CORE Figure 2 - Pin Connections (32 pin QFN with E-pad) ZL30110 Made an addition to the table. C25fo C65o ZL30110 GND (33- E-pad CORE CORE 2 Zarlink Semiconductor Inc. Data Sheet Change CORE C125o 16 C100/66o ...
Page 3
... Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1 Jitter 5.2 Jitter Generation (Intrinsic Jitter 5.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ZL30110 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
Page 4
... Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - DPLL Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Clock Oscillator Circuit Figure 6 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - Input to Output Timing for Synchronous Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 - Asynchronous Clocks Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ZL30110 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
Page 5
... Table 1 - Clock Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2 - Crystal Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ZL30110 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
Page 6
... C25do O Clock 25 MHz (LVCMOS). This is a buffered external oscillator clock, the phase and frequency accuracy of this output tracks that of the external crystal or oscillator. ZL30110 Description 6 Zarlink Semiconductor Inc. Data Sheet ...
Page 7
... GND Ground GND Ground GND Ground GND Ground GND Ground GND Internal Connection. Package E-pad, this pin is internally connected to device GND, it should be connected to GND. E-pad ZL30110 Description nominal. DC nominal. DC nominal. DC nominal. DC nominal. DC nominal. DC nominal. DC nominal. DC nominal. ...
Page 8
... Coarse Frequency Monitor Single Cycle Monitor Exceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into FreeRun mode. ZL30110 Mode select OR state machine Figure 3 - Reference Monitor Circuit 8 Zarlink Semiconductor Inc ...
Page 9
... As shown in Figure 1, the state machine controls the DPLL. 3.5 APLL The ZL30110 employ two Analog PLLs as a clock multiplying and rate conversion engine. One APLL is used to multiply the master clock (OSCi) to 125 MHz, a second APLL is used to convert the master clock (OSCi) to 100 MHz or 66 MHz clock. ...
Page 10
... When the ZL30110 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy of its freerunning local oscillator (see Figure 4). If the ZL30110 determines that its selected reference is disrupted (see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted ...
Page 11
... The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. ZL30110 11 Zarlink Semiconductor Inc. Data Sheet ...
Page 12
... When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30110, and the OSCo output should be left open as shown in Figure 5. ...
Page 13
... A typical crystal oscillator specification is shown in Table 2. 1 Frequency 2 Tolerance 3 Oscillation mode 4 Resonance mode 5 Load capacitance 6 Maximum series resistance Table 2 - Crystal Oscillator Specification ZL30110 25 MHz as required (better than +/-50ppm) fundamental parallel as required 50 Ω 13 Zarlink Semiconductor Inc. Data Sheet . ...
Page 14
... Power Up Sequence The ZL30110 requires that the 3.3 V supply is not powered up after the 1.8 V supply. This is to prevent the risk of latch-up due to the presence of protection diodes in the IO pads. Two options are given: 1. Power-up the 3.3 V supply fully first, then power up the 1.8 V supply 2. Power up the 3.3 V supply and the 1.8 V supply simultaneously, ensuring that the 3.3 V supply is never lower than a few hundred millivolts below the 1 ...
Page 15
... Input Voltage * Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 Supply current 2 Core supply current 3 Schmitt trigger Low to High threshold point 4 Schmitt trigger High to Low threshold point 5 Input leakage current ZL30110 Symbol Min. V -0.5 DD_R V -0.5 CORE_R V -0.5 PIN V -0.3 OSC I ...
Page 16
... Rise and Fall Threshold Voltage Low * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. ALL SIGNALS t t IRF, ORF Figure 7 - Timing Parameter Measurement Voltage Levels ZL30110 Sym. Min. Max 0.4 OL Sym ...
Page 17
... MHz reference input to C65o delay 5 C65o pulse width low 6 Output clock rise or fall time * Supply voltage and operating temperature are as per Recommended Operating Conditions. Outputs loaded with 30 pF. t REF<xx>P REF C65o Figure 8 - Input to Output Timing for Synchronous Clock ZL30110 Symbol t REF8kP t REF2P t REF8P t REF16P t REFW ...
Page 18
... Performance Characteristics Performance Characteristics* - Functional Characteristics DPLL capture range 1 Lock Time 2 DPLL 58 Hz Filter 3 DPLL 922 Hz Filter 4 APLL 450 kHz Filter * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30110 Symbol Min. Max M_C25D t M_C25D Symbol Min. Max. t ...
Page 19
... Supply voltage and operating temperature are as per Recommended Operating Conditions. Performance Characteristics* - Filtered Jitter Generation - RMS Characteristics 1 C25a/b/c/d/e/fo (25 MHz) - (625 kHz - Nyquist) 2 C125o (125 MHz) (625 kHz - Nyquist) * Supply voltage and operating temperature are as per Recommended Operating Conditions. ZL30110 Max. [ 0.60 0.30 cycle-to-cycle 0.20 ...
Page 20
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...